參數(shù)資料
型號: MT48LC16M16A2
廠商: Micron Technology, Inc.
英文描述: SYNCHRONOUS DRAM
中文描述: 同步DRAM
文件頁數(shù): 55/62頁
文件大小: 1517K
代理商: MT48LC16M16A2
55
256Mb: x4, x8, x16 SDRAM
256MSDRAM_E.p65
Rev. E; Pub. 3/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
256Mb: x4, x8, x16
SDRAM
SINGLE WRITE – WITH AUTO PRECHARGE
1
NOTE:
1. For this example, the burst length = 1.
2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A9, A11, and A12 =
Don
t Care
x8: A11 and A12 =
Don
t Care
x4: A12 =
Don
t Care
4. WRITE command not allowed else
t
RAS would be violated.
*CAS latency indicated in parentheses.
-7E
-75
SYMBOL*
t
CMS
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
WR
MIN
1.5
0.8
1.5
37
60
15
15
1 CLK +
7ns
MAX
MIN
1.5
0.8
1.5
44
66
20
20
1 CLK +
7.5ns
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
120,000
120,000
TIMING PARAMETERS
-7E
-75
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CKH
t
CKS
t
CMH
MIN
0.8
1.5
2.5
2.5
7
7.5
0.8
1.5
0.8
MAX
MIN
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ENABLE AUTO PRECHARGE
tCH
tCL
tCK
tRP
tRAS
tRC
tRCD
DQM/
DQML, DQMU
CKE
CK
A0-A9, A11, A12
DQ
BA0, BA1
A10
tCMH
tCMS
tAH
tAS
ROW
ROW
BANK
BANK
ROW
ROW
BANK
tWR
2
D
IN
m
COMMAND
tCMH
tCMS
NOP4
NOP4
NOP
ACTIVE
NOP4
WRITE
NOP
ACTIVE
tAH
tAS
tAH
tAS
tDH
tDS
tCKH
tCKS
NOP
NOP
COLUMN m
3
T0
T1
T2
T4
T3
T5
T6
T7
T8
T9
DON
T CARE
相關(guān)PDF資料
PDF描述
MT48LC64M4A2 SYNCHRONOUS DRAM
MT48LC4M32B2 SYNCHRONOUS DRAM
MT48LC4M32LFFC SYNCHRONOUS DRAM
MT48LC64M8A2 SYNCHRONOUS DRAM
MT48LC32M16A2 SYNCHRONOUS DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述