參數(shù)資料
型號(hào)： MT46V64M8TG-75ZL
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 51/68頁(yè)
文件大小： 2555K
代理商： MT46V64M8TG-75ZL
51
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
average refresh rate of 7.8125μs. However, an
AUTO REFRESH command must be asserted at
least once every 70.3μs; burst refreshing or
posting by the DRAM controller greater than
eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group
will not differ by more than this maximum
amount for any given device.
25. The valid data window is derived by achieving
other specifications -
t
HP (
t
CK/2),
t
DQSQ, and
t
QH (
t
HP -
t
QHS). The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: x4 = DQS with
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS
with DQ0-DQ7; and UDQS with DQ8-DQ15.
27. This limit is actually a nominal value and does
not result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
NOTES (continued)
CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge
of the input must:
a) Sustain a constant slew rate from the current
AC level through to the target AC level, V
IL
(
AC
)
or V
IH
(
AC
).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue
to maintain at least the target DC level, V
IL
(
DC
)
or V
IH
(
DC
).
29. The Input capacitance per pin group will not
differ by more than this maximum amount for
any given device.
30. JEDEC specifies CK and CK# input slew rate must
be
≥
1V/ns (2V/ns if measured differentially).
31. DQ and DM input slew rates must not deviate
from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to
t
DS and
t
DH for
each 100mv/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain.
32. V
DD
must not vary more than 4% if CKE is not
active while any bank is active.
DERATING DATA VALID WINDOW
(
t
QH -
t
DQSQ)
3.750
3.700
3.650
3.600
3.550
3.500
3.450
3.400
3.350
3.300
3.250
3.400
3.350
3.300
3.250
3.200
3.150
3.100
3.050
3.000
2.950
2.900
2.500
2.463
2.425
2.388
2.350
2.313
2.275
2.238
2.200
2.163
2.125
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
n
——
-75 @
t
CK = 10ns
——
-8 @
t
CK = 10ns
——
-75 @
t
CK = 7.5ns
——
-8 @
t
CK = 8ns
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