- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384755 > MT46V64M8TG-75ZL (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | MT46V64M8TG-75ZL |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 37/68頁 |
| 文件大?。?/td> | 2555K |
| 代理商： | MT46V64M8TG-75ZL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁當(dāng)前第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
37
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 25
PRECHARGE Command
PRECHARGE
The PRECHARGE command (Figure 25) is used to
deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (
t
RP) af-
ter the PRECHARGE command is issued. Input A10
t
IS
t
IS
No READ/WRITE
access in progress
Exit power-down mode
Enter power-down mode
CKE
CK
CK#
COMMAND
NOP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
NOP
VALID
T0
T1
T2
Ta0
Ta1
Ta2
VALID
DON
’
T CARE
determines whether one or all banks are to be
precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. When
all banks are to be precharged, inputs BA0, BA1 are
treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued to
that bank.
POWER-DOWN (CKE NOT ACTIVE)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to
be active at all times an access is in progress: from the
issuing of a READ or WRITE command until comple-
tion of the burst. Thus a clock suspend is not supported.
For READs, a burst completion is defined when the
Read Postamble is satisfied; For WRITEs, a burst
completion is defined when the Write Postamble is
satisfied.
Power-down (Figure 26) is entered when CKE is reg-
istered LOW. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down;
if power-down occurs when there is a row active in any
bank, this mode is referred to as active power-down.
Entering power-down deactivates the input and output
buffers, excluding CK, CK#, and CKE. For maximum
power savings, the DLL is frozen during precharge
power-down. Exiting power-down requires the device to
be at the same voltage and frequency as when it entered
power-down. However, power-down duration is limited
by the refresh requirements of the device (
t
REFC).
While in power-down, CKE LOW and a stable clock
signal must be maintained at the inputs of the DDR
SDRAM, while all other input signals are “Don’t Care.”
The power-down state is synchronously exited when
CKE is registered HIGH (in conjunction with a NOP or
DESELECT command). A valid executable command
may be applied one clock cycle later.
Figure 26
Power-Down
CS#
WE#
CAS#
RAS#
CKE
A10
BA0,1
HIGH
ALL BANKS
ONE BANK
BA
A0
–
A9, A11, A12
CK
CK#
BA = Bank Address (if A10 is LOW;
otherwise
“
Don
’
t Care
”
)
DON
’
T CARE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V64M8TG-8 | DOUBLE DATA RATE DDR SDRAM |
| MT46V64M8TG-8L | DOUBLE DATA RATE DDR SDRAM |
| MT48LC16M8A2 | SYNCHRONOUS DRAM |
| MT48LC2M32B2 | SYNCHRONOUS DRAM |
| MT48LC32M8A2 | SYNCHRONOUS DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V64M8TG-8 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M8TG-8L | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V8M16 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。