參數(shù)資料
型號: MT46V64M8TG-75L
廠商: Micron Technology, Inc.
英文描述: DOUBLE DATA RATE DDR SDRAM
中文描述: 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁數(shù): 58/68頁
文件大?。?/td> 2555K
代理商: MT46V64M8TG-75L
58
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
Figure 31
Data Input Timing
Figure 30
Data Output Timing -
t
AC and
t
DQSCK
CK
CK#
DQS, or LDQS/UDQS
2
T0
7
T1
T2
T3
T4
T5
T2n
T3n
T4n
T5n
T6
NOTE:
1.tDQSCK is the DQS output window relative to CK and is the
long term
component of DQS skew.
2.
DQs transitioning after DQS transition define tDQSQ window.
3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.
4.tAC is the DQ output window relative to CK, and is the
long term
component of DQ skew.
5.tLZ
(
MIN)
and tAC
(
MIN)
are the first valid signal transition.
6.tHZ
(
MAX
,and tAC
(
MAX)
are the latest valid signal transition.
7. READ command with CL = 2 issued at T0.
tRPST
tLZ
(MIN)
tDQSCK
1
(MAX)
tDQSCK
1
(MIN)
tDQSCK
1
(MAX)
tDQSCK
1
(MIN)
tHZ
(MAX)
tRPRE
DQ (Last data valid)
DQ (First data valid)
All DQs collectively
3
tAC
4
(MIN)
tAC
4
(MAX)
tLZ
(MIN)
tHZ
(MAX)
T2
T2
T2n
T3n
T4n
T5n
T2n
T2n
T3n
T3n
T4n
T4n
T5n
T5n
T3
T4
T4
T5
T5
T2
T3
T4
T5
T3
DQS
tDQSS
tDQSHtWPST
tDH
tDS
tDQSL
tDSS2
tDSH1
tDSH1
tDSS2
DM
DQ
CK
CK#
T0
3
T1
T1n
T2
T2n
T3
DI
b
NOTE:
1.tDSH
(
MIN)
generally occurs during tDQSS
(
MIN)
.
2.tDSS
(
MIN)
generally occurs during tDQSS
(
MAX)
.
3. WRITE command issued at T0.
4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
DON
T CARE
TRANSITIONING DATA
t
WPRE
t
WPRES
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