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| 型號(hào)： | MT46V64M8TG-75L |
| 廠(chǎng)商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁(yè)數(shù)： | 53/68頁(yè) |
| 文件大?。?/td> | 2555K |
| 代理商： | MT46V64M8TG-75L |
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53
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65
–
Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
NOTES (continued)
39. The voltage levels used are derived from a
minimum V
DD
level and the refernced test load.
In practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
40. V
IH
overshoot: V
IH
(MAX) = V
DD
Q+1.5V for a pulse
width
≤
3ns and the pulse width can not be
greater than 1/3 of the cycle rate.
VIL undershoot: VIL(MIN) = -1.5V for a pulse
width
≤
3ns and the pulse width can not be
greater than 1/3 of the cycle rate.
41. V
DD
and V
DDQ
must track each other.
42. This maximum value is derived from the
referenced test load. In practice, the values
obtained in a typical terminated design may
reflect up to 310ps less for
t
HZmax and the last
DVW.
t
HZ(MAX) will prevail over
t
DQSCK(MAX) +
t
RPST(MAX) condition.
43. For slew rates greater than 1V/ns the (LZ)
transition will start about 310ps earlier.
t
LZ(MIN)
will prevail over a
t
DQSCK(MIN) +
t
RPRE(MAX)
condition.
4
4. During initialization, V
DDQ
, V
TT
, and V
REF
must be
equal to or less than V
DD
+ 0.3V. Alternatively, V
TT
may be 1.35V maximum during power up, even if
V
DD
/V
DDQ
are 0 volts, provided a minimum of 42
ohms of series resistance is used between the V
TT
supply and the input pin.
Figure C
Pull-Down Characteristics
0
10
20
30
40
50
60
70
80
0.0
0.5
1.0
1.5
2.0
2.5
V
OUT
(V)
I
O
Figure D
Pull-Up Characteristics
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
0.0
0.2
0.4
0.6
0.8
1.0
V
DD
Q - V
OUT
(V)
I
O
45. The current Micron part operates below the
slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
46.
Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data
changing at every transfer.
49. Random addressing changing 100% of data
changing at every transfer.
50. CKE must be active (high) during the entire time
a refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge,
until
t
REF later.
51. IDD2N specifies the DQ, DQS, and DM to be
driven to a valid high or low logic level. IDD2Q is
similar to IDD2F except IDD2Q specifies the
address and control inputs to remain stable.
Although IDD2F, IDD2N, and IDD2Q are similar,
IDD2F is “worst case.”
52. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset,
and followed by 200 clock cycles.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT46V64M8TG-75Z | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M8TG-75ZL | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M8TG-8 | 制造商:MICRON 制造商全稱(chēng):Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
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