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參數(shù)資料
| 型號： | MT1020A |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Bluetooth Baseband Controller(藍(lán)牙技術(shù)基帶控制器) |
| 中文描述： | 藍(lán)牙基帶控制器（藍(lán)牙技術(shù)基帶控制器） |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 117K |
| 代理商： | MT1020A |
7
MT1020A
The block operates in either Interrupt or Polled modes also
supports Fly-by DMA transfers.
Interrupt Controller (INTC)
The ARM7TDMI core accepts two types of interrupt:
Normal (IRQ) and Fast (FIQ). All Interrupts can be switched
between types, depending upon the relative priorities
required. The INTC is the central control logic that decodes
the priority level and handles interrupt request signals from
a total of 8 fixed predefined sources within the Firefly MF1
Core and two external sources, Gpio<7:6>. External
interrupts can be set for edge or level sensitivity with a
polarity option. To minimize interrupt latency, there is a
hard-wired priority scheme for each channel for both FIQ
and IRQ; alternatively this can be ignored and the priority
assessment handled in software.
Timers
Two dual independent 32-bit timer/counters, with an 8-bit
prescaler capability for each counter, are provided (Timers
1A, 1B, 2A and 2B). These are synchronous to the system
clock and may be polled, or set up to generate interrupts
on over-run, with auto-reload.
DMA Controller
Two DMA engines are available in the controller. These
may be configured as a pair to provide a memory-to-
memory DMA capability between any two locations in the
ARM7TDMI memory space. Alternatively, they may be
used independently for fly-by transfers between off-core
requesters and either on-core or off-core locations. Single
or multiple byte transfers (Demand or Burst Mode) are
supported and may be word, half-word or byte wide.
Universal Asynchronous Receiver Transmitter (UART1)
The full duplex asynchronous channel provides an RS232
type interface, which supports both hardware handshaking
and XON/XOFF software protocols. The Receive and
Transmit channels are double buffered. UART1 may be
polled, or may use an interrupt scheme for module bus
transfers. An internal baud rate generator can provide
selectable data rates, derived from on-chip sources for an
Rx/Tx pair. Directly triggered DMA transfers with the UART
are also possible without the need for CPU intervention.
SYSTEM MEMORY
System memory is available on the UIM Bus. The MT1020
has 20KB internal static RAM, for program variable storage.
An external ROM/FLASH is required to store the Link
Controller and Link Manager protocol code. Future versions
of the MT020 will have on-chip ROM, with potential storage
for application code.
System Debug Options
The Firefly MF1 Core allows for three sophisticated meth-
ods of hardware and software debug. The designer should
choose which methods are required. The options are:
G
Embedded ICE
G
Angel
Debug Monitor
G
Logic Analyser coupled with an Inverse Assembler and
Mitel
’
s Diagnostic Broadcast feature
BASEBAND PROTOCOL STACK
The Mitel baseband protocol stack software complies with
the Bluetooth Specification v1
·
0, and implements the
following features:
Link Controller
The Link Controller includes muiti-point capability, support
for multi-slot packets, and Authentication and Encryption.
Link Manager
Supports Park, Hold and Sniff modes for reduced power
consumption.
Host Controller Interface
Operates via USB or UART interface, supporting ACL
(asynchronous) and SCO (synchronous) data types.
Thumb is the registered trademark of ARM Limited.
ARM7TDMI, Angel and EmbeddedlCE are the trademarks of ARM Limited.
MICROWIRE is the registered trademark of National Semiconductor
Corporation.
Mitel MT1020 is a registered trademark of MITEL Corporation
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