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參數(shù)資料
| 型號(hào)： | MT1020A |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Bluetooth Baseband Controller(藍(lán)牙技術(shù)基帶控制器) |
| 中文描述： | 藍(lán)牙基帶控制器（藍(lán)牙技術(shù)基帶控制器） |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大小： | 117K |
| 代理商： | MT1020A |
6
MT1020A
CIRCUIT DESCRIPTION
General
The MT1020A consists of the Mitel Semiconductor Firefly
embedded microcontroller core, the
Bluetooth
Baseband
Peripheral block including audio CODEC, program
memory, a general purpose ADC, USB and UART host
interfaces. The MT1020A, when used with the Philsar
PH2401 radio transceiver, forms a complete low power
Bluetooth
solution.
Low Power Architecture
The architecture is designed for ultra low power
applications. This is achieved by:
G
Minimising the processor overhead, allowing internal
system clock speeds to be reduced to as low as 5MHz.
G
Having a dedicated
Bluetooth
bus for data packet DMA
transfers.
G
A system partition that decodes
Bluetooth
packets in
hardware.
G
Operating internal core with a 2V supply.
G
Low-power CODEC for voice applications.
Bluetooth
BASEBAND PERIPHERAL
The
Bluetooth
Baseband Peripheral (BBP) sub-system
performs all time critical Bluetooth operations, with minimal
processor overhead. The BBP is a simple peripheral device
on the Up-Integration Module (UIM) Bus AND consists of
the following blocks.
Bus Interface
The Bus Interface block is a simple interface, which allows
communication between the processor via the UIM bus
and the Bluetooth Baseband Peripheral (BBP). The BBP
has a dedicated BT bus for all Bluetooth payload data
transfers.
Bluetooth
Link Controller
The
Bluetooth
Link Controller controls the
Bluetooth
radio.
The radio interface comrnunicates with the Philsar
PH2401 radio transceiver. Payload data is assembled/
extracted into/from data packets for/from transmit/received
data. Packets are assembled/decoded with preamble, sync
words, headers and CRCs. Data whitening is performed;
encryption is optional.
Queue Manager Block
This block performs intelligent DMA transfers between a
dedicated
Bluetooth
data buffer RAM and the
Bluetooth
link controller, the USB or serial host and the voice interface.
It understands and translates between different
Bluetooth
packet formats, and performs payload data queue
management.
Buffer RAM - 12KBytes
This memory is dedicated storage for Bluetooth packets
and variables. It is not used for system information.
Host Interfaces
The host interfaces are the standard USB and a high speed
host UART.
Audio CODEC
The full duplex CODEC includes a microphone amplifier
and earpiece driver, together with filtering to ITU-T G712.
A digital conversion block translates between linear PCM,
A-law and
μ
-law log PCM and CVSD.
FIREFLY EMBEDDED MICROCONTROLLER CORE
The Firefly MF1 Embedded MicrocontrollerCore consists
of an ARM7TDMI CPU, a proprietary purpose built Inter-
Module bus and a number of functional blocks. For further
details, refer to Mitel
’
s Firefly MF1 Core Design Manual,
Mitel Semiconductor publication number DM5003
ARM7TDMI Processor
The ARM7TDMI RISC processor contains the ARM7 32- bit
core and with the Thumb
instruction de-compressor
supporting 16-bit instructions, debug extensions, fast
multiplier and the ICEBreaker extension. The ARM7TDMI
interfaces to the Inter-Module bus.
Peripheral Controller
The Peripheral Controller is the main gateway between
the internal and external bus systems. It allows dynamic
bus sizing and generates all control signals to access pe-
ripheral components.
The Peripheral Controller supports fly-by DMA between
ail combinations of internal and external modes.
Serial I/0
The Serial (Bsio) I/0 block supports the serial interface to
a variety of external devices, such as serial EEPROM,
NVRAM and Flash. It is compatible with two common
interfaces:
G
MICROWIRE
for use with memory and peripheral
devices supporting the MICROWIRE standard.
G
SPI microcontroller serial interface.
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