參數(shù)資料
型號: MSC7116
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC
中文描述: 低成本16位數(shù)字信號處理器與DDR控制器和10/100 Mbps以太網(wǎng)MAC
文件頁數(shù): 46/56頁
文件大?。?/td> 719K
代理商: MSC7116
MSC7116 10/100 Mbps Ethernet MAC Data Sheet, Rev. 11
Hardware Design Considerations
Freescale Semiconductor
46
3.3.6
Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
P
TOTAL
= 287 + (4
×
3.83) + 326.3 + (10
×
7.19) + 64 = 764.52 mW
Eqn. 13
3.4
Reset and Boot
This section describes the recommendations for configuring the MSC7116 at reset and boot.
3.4.1
Reset Circuit
HRESET
is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as
HRESET
, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7116 output
current, the pull-up value should not be too small (a 1 K
Ω
pull-up resistor is used in the MSC711xADS reference design).
3.4.2
Reset Configuration Pins
Table 34
shows the MSC7116 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET
. For details, refer to the Reset chapter of the
MSC711x Reference Manual
.
Table 34. Reset Configuration Signals
Signal
Description
Settings
BM[3–0]
SWTE
Determines boot mode.
Determines watchdog functionality.
See
Table 35
for details.
0
Watchdog timer disabled.
1
Watchdog timer enabled.
0
Host Data strobes active low.
1
Host Data strobes active high.
0
HDI16 port configured for 16-bit operation.
1
HDI16 port configured for 8-bit operation.
HDSP
Configures HDI16 strobe polarity.
H8BIT
Configures HDI16 operation mode.
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