參數(shù)資料
型號： MSC7113VM800
廠商： Freescale Semiconductor
文件頁數(shù)： 48/60頁
文件大?。?/td> 0K
描述： IC DSP PROCESSOR 16BIT 400MAPBGA
標準包裝： 90
系列： StarCore
類型： SC1400 內(nèi)核
接口： 主機接口，I²C，UART
時鐘速率： 200MHz
非易失內(nèi)存： 外部
芯片上RAM： 208kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.20V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 400-LFBGA
供應商設備封裝： 400-MAPBGA（17x17）
包裝： 托盤
MSC7113 Data Sheet, Rev. 11
Hardware Design Considerations
Freescale Semiconductor
52
3.4.2
Reset Configuration Pins
Table 34 shows the MSC7113 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET
. For details, refer to the Reset chapter of the MSC711x Reference Manual.
3.4.3
Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Using this input
clock, the system initializes using the boot loader program that resides in the internal ROM. After initialization, the
DSP core can enable the PLL and start the device operating at a higher speed. The MSC7113 can boot from an
external host through the HDI16 or download a user program through the I2C port. The boot operating mode is set
by configuring the BM[1–0] signals sampled at the rising edge of PORESET, as shown in Table 35.
3.4.3.1
HDI16 Boot
If the MSC7113 device boots from an external host through the HDI16, the port is configured as follows:
Operate in Non-DMA mode.
Operate in polled mode on the device side.
Operate in polled mode on the external host side.
External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
8- or 16-bit mode as specified by the H8BIT pin.
Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note:
When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
Table 34. Reset Configuration Signals
Signal
Description
Settings
BM[1–0]
Determines boot mode.
0
Boot from HDI16 port.
01
Boot from I2C.
1x
Reserved.
SWTE
Determines watchdog functionality.
0
Watchdog timer disabled.
1
Watchdog timer enabled.
HDSP
Configures HDI16 strobe polarity.
0
Host Data strobes active low.
1
Host Data strobes active high.
H8BIT
Configures HDI16 operation mode.
0
HDI16 port configured for 16-bit operation.
1
HDI16 port configured for 8-bit operation.
Table 35. Boot Mode Settings
BM1
BM0
Boot Source
0
External host via HDI16 with the PLL disabled.
01
I2C.
1
0
External host via the HDI16 with the PLL enabled.
1
Reserved.
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