參數(shù)資料
型號： MR80C52CXXX-25SB
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 8/60頁
文件大?。?/td> 5137K
代理商： MR80C52CXXX-25SB
16
8266D-MCU Wireless-06/12
ATmega128RFA1
interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit
is automatically set when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that
sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the
actual Interrupt Vector in order to execute the interrupt handling routine, and hardware
clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a
logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while
the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and
remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if
one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared,
the corresponding Interrupt Flag(s) will be set and remembered until the Global
Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present.
These interrupts do not necessarily have Interrupt Flags. If the interrupt condition
disappears before the interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt
routine, nor restored when returning from an interrupt routine. This must be handled by
software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately
disabled. No interrupt will be executed after the CLI instruction, even if it occurs
simultaneously with the CLI instruction. The following example shows how this can be
used to avoid interrupts during the timed EEPROM write sequence.
Assembly Code Example
in r16, SREG ; store SREG value
cli ; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16 ; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
__disable_interrupt();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
When using the SEI instruction to enable interrupts, the instruction following SEI will be
executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei ; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
相關(guān)PDF資料
PDF描述
MR80C52UXXX-25 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQCC44
IS80C32U-S 8-BIT, 20 MHz, MICROCONTROLLER, PQCC44
IV80C52UXXX-S 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44
IS80C52UFXXX-S:R 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44
IS80C52UXXX-25:R 8-BIT, MROM, 25 MHz, MICROCONTROLLER, PQCC44
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