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| 型號： | MR1S16AYS35 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PDSO44 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-44 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 235K |
| 代理商： | MR1S16AYS35 |
MR0A16A Advanced Information Data Sheet, Rev. 2
14
Freescale Semiconductor
Timing Specifications
Table 12. Write Cycle Timing 3 (LB/UB Controlled)
1, 2, 3, 4, 5, 6
Parameter
Symbol
Min
Max
Unit
Write cycle time7
tAVAV
35
—
ns
Address set-up time
tAVBL
0—
ns
Address valid to end of write (G high)
tAVBH
18
—
ns
Address valid to end of write (G low)
tAVBH
20
—
ns
Byte pulse width (G high)
tBLEH
tBLWH
15
—
ns
Byte pulse width (G low)
tBLEH
tBLWH
15
—
ns
Data valid to end of write
tDVBH
10
—
ns
Data hold time
tBHDX
0—
ns
Write recovery time
tBHAX
12
—
ns
NOTES:
1
A write occurs during the overlap of E low and W low.
2
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
3
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
4
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
5
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
6
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
7
All write cycle timings are referenced from the last valid address to the first transition address.
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