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參數(shù)資料
| 型號： | MR1S16AYS35 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PDSO44 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-44 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 235K |
| 代理商： | MR1S16AYS35 |
MR0A16A Advanced Information Data Sheet, Rev. 2
10
Freescale Semiconductor
Timing Specifications
Write Mode
Table 10. Write Cycle Timing 1 (W Controlled)1, 2, 3, 4, 5
Parameter
Symbol
Min
Max
Unit
Write cycle time6
tAVAV
35
—
ns
Address set-up time
tAVWL
0—
ns
Address valid to end of write (G high)
tAVWH
18
—
ns
Address valid to end of write (G low)
tAVWH
20
—
ns
Write pulse width (G high)
tWLWH
tWLEH
15
—
ns
Write pulse width (G low)
tWLWH
tWLEH
15
—
ns
Data valid to end of write
tDVWH
10
—
ns
Data hold time
tWHDX
0—
ns
Write low to data Hi-Z7, 8, 9
tWLQZ
012
ns
Write high to output active7, 8, 9
tWHQX
3—
ns
Write recovery time
tWHAX
12
—
ns
NOTES:
1
A write occurs during the overlap of E low and W low.
2
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
3
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
4
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
5
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
6
All write cycle timings are referenced from the last valid address to the first transition address.
7
This parameter is sampled and not 100% tested.
8
Transition is measured
±200 mV from steady-state voltage.
9
At any given voltage or temperature, tWLQZ max < tWHQX min.
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