- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359660 > MR1A16AYS35 (飛思卡爾半導體(中國)有限公司) 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM PDF資料下載
參數(shù)資料
| 型號： | MR1A16AYS35 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM |
| 中文描述： | 64K的x 16位的3.3V異步磁阻隨機存取內(nèi)存 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 148K |
| 代理商： | MR1A16AYS35 |
Timing Specifications
MR0A16A Advanced Information Data Sheet, Rev. 0
Freescale Semiconductor
13
Table 12. Write Cycle Timing 3 (LB/UB Controlled)
1, 2, 3, 4, 5, 6
Parameter
Symbol
t
AVAV
t
AVBL
t
AVBH
t
AVBH
t
BLEH
t
BLWH
t
BLEH
t
BLWH
t
DVBH
t
BHDX
t
BHAX
Min
35
0
18
20
Max
—
—
—
—
Unit
ns
ns
ns
ns
Write cycle time
7
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Byte pulse width (G high)
15
—
ns
Byte pulse width (G low)
15
—
ns
Data valid to end of write
Data hold time
Write recovery time
10
0
12
—
—
—
ns
ns
ns
NOTES:
1
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
2
3
4
5
6
7
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MR1S08AYS35 | 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM |
| MR1S16AYS35 | 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM |
| MR2A08AYS35 | 64K x 16-Bit 3.3-V Asynchronous Magnetoresistive RAM |
| MC68HC908JB12DW | This section updates data sheet information and introduces the 20-pin SOIC |
| MC68HC908JB12JDW | This section updates data sheet information and introduces the 20-pin SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR1D100R00TST | 制造商:Vishay Semiconductors 功能描述: |
| MR1FB10L0 | 制造商:SEI Stackpole Electronics Inc 功能描述:RES 10M OHM 1% 1W 50PPM/ C TO 400PPM/ C AXL TH - Bulk 制造商:SEI Stackpole Electronics Inc 功能描述:Res Metal Film 0.01 Ohm 1% 1W ±50ppm/°C to ±400ppm/°C Molded AXL Thru-Hole Bulk |
| MR1FB20L0 | 制造商:SEI Stackpole Electronics Inc 功能描述:RES 1W 0.02 OHMS 1% - Bulk |
| MR1FB30L0 | 制造商:SEI Stackpole Electronics Inc 功能描述:RES 1W 0.03 OHMS 1% - Bulk |
| MR1FB50L0 | 制造商:SEI Stackpole Electronics Inc 功能描述:RES 1W 0.05 OHMS 1% - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。