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參數(shù)資料
| 型號(hào)： | MPC92432FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 1360 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MPC92432FAR2 |
Advanced Clock Drivers Devices
12
Freescale Semiconductor
MPC92432
Note that a PLL configuration obtained by the parallel
interface can be read through I2C independent on the current
programming mode (parallel or serial). Refer to I2C —
Register Access in Parallel Mode for additional information
on how to read a PLL startup configuration through the I2C
interface.
Starting-Up Using the Parallel Interface
The simplest way to use the MPC92432 is through the
parallel interface. The serial interface pins (SDA, SDL, and
ADDR[1:0]) can be left open and PLOAD is set to logic low.
After the release of MR and at any other time the PLL/output
frequency configuration is directly set to through the M[9:0],
NA[2:0], NB, and P pins.
Start-Up Using the Serial (I2C) Interface
Figure 4. Start-Up Using I2C Interface
Set PLOAD = 1, CLK_STOPx = L and leave the parallel
interface pins (M[9:0], NA[2:0], N, and P) open. The PLL
dividers are configured by the default configuration at the low-
to-high transition of MR. This initial PLL configuration can be
re-programmed to the final VCO frequency at any time
through the serial interface. After the PLL achieved lock at the
desired VCO frequency, enable the outputs by setting
CLK_STOPx = H. PLL lock and re-lock (after any
configuration change through M or P) is indicated by LOCK
being asserted.
LOCK Detect
The LOCK detect circuitry indicates the frequency-lock
status of the PLL by setting and resetting the pin LOCK and
register bit LOCK simultaneously. The LOCK status is
asserted after the PLL acquired frequency lock during the
startup and is immediately deasserted when the PLL lost
lock, for instance when the reference clock is removed. The
PLL may also loose lock when the PLL feedback-divider M or
pre-divider P is changed or the DEC/INC command is issued.
The PLL may not loose lock as a result of slow reference
frequency changes. In any case of loosing LOCK, the PLL
attempts to re-lock to the reference frequency. LOCK and re-
lock of the PLL is indicated by the LOCK signal after a delay
of TBD cycles to prevent signaling temporary PLL locks
during frequency transitions.
Output Clock Stop
Asserting CLK_STOPx will stop the respective output
clock in logic low state. The CLK_STOPx control is internally
synchronized to the output clock signal, therefore, enabling
and disabling outputs does not produce runt pulses. See
Figure 5. The clock stop controls of the QA and QB outputs
are independent on each other. If the QB runs at half of the
QA output frequency and both outputs are enabled at the
same time, the first clock pulse of QA may not appear at the
same time of the first QB output. (See Figure 6.) Concident
rising edges of QA and QB stay synchronous after the
assertion and de-assertion of the CLK_STOPx controls.
Asserting MR always resets the output divider to a logic low
output state, with the risk of producing an output runt pulse.
Figure 5. Clock Stop Timing for NB = 0 (fQA = fQB)
Figure 6. Clock Stop Timing for NB = 1 (fQA = 2 fQB)
VCC
MR
P, M, N
PLOAD
LOCK
CLK_STOPx
QA, QB
Stable & Valid
Selects I2C
Acquiring Lock
PLL Lock
Disabled (Low)
tPLH
Active
CLK_STOPx
Qx
(Disable)
(Enable)
tP_DIS
tP_EN
CLK_STOPA,B
QA
QB
(Disable)
(Enable)
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| MPC92433 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:1428 MHz Dual Output LVPECL Clock Synthesizer |
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| MPC92439AC | 功能描述:IC SYNTHESIZER LVPECL 32-LQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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