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參數(shù)資料
| 型號(hào)： | MPC92432FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 1360 MHz, OTHER CLOCK GENERATOR, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MPC92432FAR2 |
Advanced Clock Drivers Devices
4
Freescale Semiconductor
MPC92432
Table 2. Function Table
Control
Default(1)
1. Default states are set by internal input pull-up or pull-down resistors of 75 k
.
01
Inputs
REF_SEL
1
Selects REF_CLK input as PLL reference clock
Selects the XTAL interface as PLL reference clock
M[9:0]
01 1111 0100b(2)
2. If fREF = 16 MHz, the default configuration will result in a output frequency of 250 MHz.
PLL feedback divider (10-bit) parallel programming interface
NA[2:0]
010
PLL post-divider parallel programming interface. See Table 9
NB
0
PLL post-divider parallel programming interface. See Table 10
P
1
PLL pre-divider parallel programming interface. See Table 8
PLOAD
0
Selects the parallel programming interface. The
internal PLL divider settings (M, NA, NB and P) are
equal to the setting of the hardware pins. Leaving
the M, NA, NB and P pins open (floating) results in a
default PLL configuration with fOUT = 250 MHz. See
application/programming section.
Selects the serial (I2C) programming interface. The
internal PLL divider settings (M, NA, NB and P) are
set and read through the serial interface.
ADR[1:0]
00
Address bit = 0
Address bit = 1
SDA, SCL
BYPASS
1
PLL function bypassed
fQA = fREF ÷ NA and
fQB = fREF÷ (NA NB)
PLL function enabled
fQA = (fREF ÷ P) M ÷ NA and
fQB = (fREF ÷ P) M ÷ (NA NB)
TEST_EN
0
Application mode. Test mode disabled.
Factory test mode is enabled
CLK_STOPx
1Output Qx is disabled in logic low state.
Synchronous disable is only guaranteed if NB = 0.
Output Qx is synchronously enabled
MR
The device is reset. The output frequency is zero
and the outputs are asynchronously forced to logic
low state.
After releasing reset (upon the rising edge of MR
and independent on the state of PLOAD), the
MPC92432 reads the parallel interface (M, NA, NB
and P) to acquire a valid startup frequency
configuration. See application/programming section.
The PLL attempts to lock to the reference signal.
The tLOCK specification applies.
Outputs
LOCK
PLL is not locked
PLL is frequency locked
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