參數(shù)資料
型號： MPC8567VTAUJJ
廠商： Freescale Semiconductor
文件頁數(shù)： 123/139頁
文件大?。?/td> 0K
描述： MPU POWERQUICC III 1023-PBGA
標準包裝： 1
系列： MPC85xx
處理器類型： 32-位 MPC85xx PowerQUICC III
速度： 1.333GHz
電壓： 1.1V
安裝類型： 表面貼裝
封裝/外殼： 1023-BBGA，F(xiàn)CBGA
供應商設備封裝： 1023-FCPBGA（33x33）
包裝： 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
84
Freescale Semiconductor
Serial RapidIO
15.7
Receiver Specifications
LP-Serial receiver electrical and timing specifications are stated in the text and tables of this section.
Receiver input impedance shall result in a differential return loss better that 10 dB and a common mode
return loss better than 6 dB from 100 MHz to (0.8)*(Baud Frequency). This includes contributions from
on-chip circuitry, the chip package and any off-chip components related to the receiver. AC coupling
components are included in this requirement. The reference impedance for return loss measurements is
100
Ω resistive for differential return loss and 25 Ω resistive for common mode.
Table 60. Transmitter Differential Output Eye Diagram Parameters
Transmitter Type
VDIFFmin
(mV)
VDIFFmax
(mV)
A (UI)
B (UI)
1.25 GBaud short range
250
500
0.175
0.39
1.25 GBaud long range
400
800
0.175
0.39
2.5 GBaud short range
250
500
0.175
0.39
2.5 GBaud long range
400
800
0.175
0.39
3.125 GBaud short range
250
500
0.175
0.39
3.125 GBaud long range
400
800
0.175
0.39
Table 61. Receiver AC Timing Specifications—1.25 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
VIN
200
1600
mV p-p
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
—
UI p-p
Measured at receiver
Combined Deterministic and Random
Jitter Tolerance
JDR
0.55
—
UI p-p
Measured at receiver
Total Jitter Tolerance1
JT
0.65
—
UI p-p
Measured at receiver
Multiple Input Skew
SMI
—
24
ns
Skew at the receiver input
between lanes of a multilane
link
Bit Error Rate
BER
—
10–12
——
Unit Interval
UI
800
ps
+/– 100 ppm
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 54. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
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