參數(shù)資料
型號: MPC8567VTAUJJ
廠商: Freescale Semiconductor
文件頁數(shù): 104/139頁
文件大?。?/td> 0K
描述: MPU POWERQUICC III 1023-PBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC85xx
處理器類型: 32-位 MPC85xx PowerQUICC III
速度: 1.333GHz
電壓: 1.1V
安裝類型: 表面貼裝
封裝/外殼: 1023-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1023-FCPBGA(33x33)
包裝: 托盤
MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1
Freescale Semiconductor
67
High-Speed Serial Interfaces (HSSI)
Figure 44 shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with MPC8568 SerDes reference clock
input’s DC requirement.
Figure 44. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
Figure 45 shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common mode voltage is higher than the MPC8568 SerDes reference clock
input’s allowed range (100 to 400mV), AC-coupled connection scheme must be used. It assumes the
LVDS output driver features 50-
Ω termination resistor. It also assumes that the LVDS transmitter
establishes its own common mode level without relying on the receiver or other external component.
Figure 45. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
50
Ω
50
Ω
SD_REF_CLK
Clock Driver
100
Ω differential PWB trace
Clock driver vendor dependent
source termination resistor
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
HCSL CLK Driver Chip
33
Ω
33
Ω
Total 50
Ω. Assume clock driver’s
output impedance is about 16
Ω.
MPC8568E
CLK_Out
50
Ω
50
Ω
SD_REF_CLK
Clock Driver
100
Ω differential PWB trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVDS CLK Driver Chip
10 nF
MPC8568E
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MPC8568E-MDS-PB 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8568E FAMILY ADS RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓:
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