參數(shù)資料
型號: MPC8379E-MDS-PB
廠商: Freescale Semiconductor
文件頁數(shù): 23/117頁
文件大?。?/td> 0K
描述: BOARD PROCESSOR FOR MDS S
標準包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8379
所含物品:
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
Freescale Semiconductor
13
4
Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the chip. Note that the
PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether
the device is configured as a host or agent device. CLKIN is used when the device is in host mode.
4.1
DC Electrical Characteristics
This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
eTSEC I/O
Load =
25 pf
MII or RMII
0.02
W
Multiply by
number of
interfaces used.
RGMII or
RTBI
0.05
W
USB
(60MHz
Clock)
12 Mbps
0.01
W
480 Mbps
0.2
W
SerDes
per lane
0.029
W
Other I/O
0.01
W
Note: The values given are for typical, and not worst case, switching.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Note
Input high voltage
VIH
2.7
OVDD + 0.3
V
Input low voltage
VIL
–0.3
0.4
V
CLKIN Input current
0 V
≤ VIN ≤ OVDD
IIN
—± 10
μA—
PCI_CLK Input current
0 V
≤ VIN ≤ 0.5 V or
OVDD – 0.5 V ≤ VIN ≤ OVDD
IIN
—± 30
μA—
Note:
1. In PCI agent mode, this specification does not comply with
PCI 2.3 Specification.
Table 6. Typical I/O Power Dissipation (continued)
Interface
Parameter
GVDD
(1.8 V)
GVDD/LBVDD
(2.5 V)
OVDD
(3.3 V)
LVDD
(3.3 V)
LVDD
(2.5 V)
L[1,2]_
nVDD
(1.0 V)
Unit
Comments
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