參數(shù)資料
型號(hào): MPC8377VRANGA
廠商: Freescale Semiconductor
文件頁數(shù): 98/127頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II 800MHZ 689PBGA
標(biāo)準(zhǔn)包裝: 27
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 800MHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 689-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 689-TEPBGA II(31x31)
包裝: 托盤
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
72
Freescale Semiconductor
16.3
Differential Receiver (Rx) Input Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.
16.3.1
Gen1i/1.5G Receiver Specifications
This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA
interface.
This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA
interface.
Total jitter
fC3dB =fBAUD/1667
USATA_TXTJfB/1667
0.55
UIp-p
Deterministic jitter
fC3dB =fBAUD/10
USATA_TXDJfB/10
0.17
UIp-p
Deterministic jitter
fC3dB =fBAUD/500
USATA_TXDJfB/500
0.19
UIp-p
Deterministic jitter
fC3dB =fBAUD/1667
USATA_TXDJfB/1667
0.35
UIp-p
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
Table 59. Gen1i/1.5G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Differential input voltage
VSATA_RXDIFF
240
500
600
mVp-p
Differential Rx input impedance
ZSATA_RXSEIM
85
100
115
Ω
Note:
1. Voltage relative to common of either signal comprising a differential pair.
Table 60. Gen 1i/1.5G Receiver AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Unit interval
TUI
666.4333
666.667
670.2333
ps
Total jitter, data-data
5UI
USATA_TXTJ5UI
0.43
UIp-p
Total jitter, data-data
250 UI
USATA_TXTJ250UI
0.60
UIp-p
Deterministic jitter, data-data
5UI
USATA_TXDJ5UI
0.25
UIp-p
Table 58. Gen 2i/3G Transmitter AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
Note
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