MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
90
Freescale Semiconductor
5 Parallelism measurement should exclude any effect of mark on top surface of package.
22.2
Pinout Listings
This table provides the pinout listing for the TePBGA II package.
Table 72. TePBGA II Pinout Listing
Signal
Package Pin Number
Pin Type
Power Supply
Note
Clock Signals
CLKIN
K24
I
OVDD
—
PCI_CLK/PCI_SYNC_IN
C10
I
OVDD
—
PCI_SYNC_OUT
N24
O
OVDD
PCI_CLK0
L24
O
OVDD
—
PCI_CLK1
M24
O
OVDD
—
PCI_CLK2
M25
O
OVDD
—
PCI_CLK3
M26
O
OVDD
—
PCI_CLK4
L26
O
OVDD
—
RTC/PIT_CLOCK
AF11
I
OVDD
—
DDR SDRAM Memory Interface
MA0
U3
O
GVDD
—
MA1
U1
O
GVDD
—
MA2
T5
O
GVDD
—
MA3
T3
O
GVDD
—
MA4
T2
O
GVDD
—
MA5
T1
O
GVDD
—
MA6
R1
O
GVDD
—
MA7
P2
O
GVDD
—
MA8
P1
O
GVDD
—
MA9
N4
O
GVDD
—
MA10
V3
O
GVDD
—
MA11
M5
O
GVDD
—
MA12
N1
O
GVDD
—
MA13
M2
O
GVDD
—
MA14
M1
O
GVDD
—
MBA0
U5
O
GVDD
—
MBA1
U4
O
GVDD
—