參數(shù)資料
型號(hào)： MPC8315ECVRAGDA
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 56/106頁(yè)
文件大?。?/td> 0K
描述： MPU POWERQUICC II PRO 620-PBGA
標(biāo)準(zhǔn)包裝： 36
系列： MPC83xx
處理器類型： 32-位 MPC83xx PowerQUICC II Pro
速度： 400MHz
電壓： 1V
安裝類型： 表面貼裝
封裝/外殼： 620-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 620-PBGA（29x29）
包裝： 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
53
High-Speed Serial Interfaces (HSSI)
Figure 38. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5V and 2.0V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(VOD) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
between 500 mV and –500 mV, in other words, VOD is 500 mV in one phase and –500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential voltage (VDIFFp-p)
is 1000 mV p-p.
15.2
SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK
for PCI Express and SGMII interface.
The following sections describe the SerDes reference clock requirements and some application
information.
15.2.1
SerDes Reference Clock Receiver Characteristics
Figure 39 shows a receiver reference diagram of the SerDes reference clocks.
The supply voltage requirements for XCOREVDD are specified in Table 1 and Table 2.
SerDes Reference Clock Receiver Reference Circuit Structure
— The SD_REF_CLK and SD_REF_CLK are internally AC-coupled differential inputs as shown
in Figure 39. Each differential clock input (SD_REF_CLK or SD_REF_CLK) has a 50-
termination to XCOREVSS followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
Differential Mode and Single-ended Mode description below for further detailed requirements.
Differential Swing, VID or VOD = A - B
A Volts
B Volts
TXn or RXn
Differential Peak Voltage, VDIFFp = |A - B|
Differential Peak-Peak Voltage, VDIFFpp = 2*VDIFFp (not shown)
Vcm = (A + B) / 2
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