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參數(shù)資料
型號: MPC8315ECVRAGDA
廠商: Freescale Semiconductor
文件頁數(shù): 21/106頁
文件大?。?/td> 0K
描述: MPU POWERQUICC II PRO 620-PBGA
標準包裝: 36
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤
供應商設備封裝: 620-PBGA(29x29)
包裝: 托盤
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
21
DDR and DDR2 SDRAM
This figure shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (tDISKEW)
Figure 6. Timing Diagram for tDISKEW
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is
the absolute value of tCISKEW.
3. Memory controller ODT value of 150
is recommended.
Table 19. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (2.5V ± 200 mV)
Parameter
Symbol
Min
Max
Unit
Note
Controller Skew for MDQS—MDQ
266 MHz
200 MHz
tCISKEW
–750
–1250
750
1250
ps
1, 2
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit to
be captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW =+/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
Table 18. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of (1.8 V± 100 mV)
Parameter
Symbol
Min
Max
Unit
Note
MCK[n]
tMCK
MDQ[x]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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