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參數(shù)資料
| 型號(hào)： | MPC8260CZUHFBC |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 166 MHz, RISC PROCESSOR, PBGA480 |
| 封裝： | 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480 |
| 文件頁(yè)數(shù)： | 23/48頁(yè) |
| 文件大?。?/td> | 688K |
| 代理商： | MPC8260CZUHFBC |
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MOTOROLA
MPC826xA (HiP4) Family Hardware Specications
3
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Features
Figure 1 shows the block diagram for the HiP4 superset device, the MPC8266A.
Figure 1. MPC8266A Block Diagram
1.1
Features
The major features of the MPC826xA family are as follows:
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic (1.8 V) and for I/O (3.3V)
16 Kbytes
G2 Core
I-Cache
I-MMU
16 Kbytes
D-Cache
D-MMU
Communication Processor Module (CPM)
Timers
Parallel I/O
Baud Rate
Generators
32 Kbytes
32-bit RISC Microcontroller
and Program ROM
Serial
DMAs
4 Virtual
IDMAs
60x-to-PCI
Bridge2,3
Bridge
Memory Controller
Clock Counter
System Functions
System Interface Unit
(SIU)
Local Bus
32 bits, up to 83 MHz
PCI Bus2,3
32 bits, up to 66 MHz
or
MCC1
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I2C
Serial Interface
3 MII
2 UTOPIA
Ports
60x Bus
1. MPC8264A
2. MPC8265A
3. MPC8266A
Notes:
Microcode
IMA1,3
Dual-Port RAM
Interrupt
Controller
Time Slot Assigner
TC Layer Hardware1,3
8 TDM Ports
Non-Multiplexed
I/O
60x-to-Local
Bus Interface Unit
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