參數(shù)資料
型號(hào)： MPC8260CZUHFBC
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 166 MHz, RISC PROCESSOR, PBGA480
封裝： 37.50 X 37.50 MM, 1.55 MM HEIGHT, 1.27 MM PITCH, TBGA-480
文件頁(yè)數(shù)： 10/48頁(yè)
文件大小： 688K
代理商： MPC8260CZUHFBC
18
MPC826xA (HiP4) Family Hardware Specications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Electrical and Thermal Characteristics
Figure 9 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 9. Parity Mode Diagram
Figure 10 shows signal behavior in MEMC mode.
Figure 10. MEMC Mode Diagram
NOTE
Generally, all MPC826xA bus and system output signals are driven from
the rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is
divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the
rising edge, and T3 at the falling edge, of CLKin. However, the spacing of
T2 and T4 depends on the PLL clock ratio selected, as shown in Table 13.
CLKin
DATA bus, ECC, and PARITY mode input signals
DP mode input signal
DP mode output signal
sp13
sp10
sp14
sp10
sp33b/sp30
CLKin
V_CLK
Memory controller signals
sp34/sp30
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