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MOTOROLA
MPC823 USER’S MANUAL
15-1
MEMORY
CONTROLLER
15
SECTION 15
MEMORY CONTROLLER
The memory controller is responsible for controlling a maximum of eight memory banks
shared between a general-purpose chip-select machine and a pair of sophisticated
user-programmable machines. It supports a glueless interface to SRAM, EPROM, flash
EPROM, regular DRAM devices, self-refresh DRAMs, extended data output DRAM devices,
synchronous DRAMs, and other peripherals. This flexible memory controller allows you to
implement memory systems with very specific timing requirements. It supports external
address multiplexing, periodic timers, and timing generation for row address and column
address strobes to allow for a glueless interface to DRAM devices. The periodic timers allow
refresh cycles to be initiated while the address muxing provides row and column addresses.
You can define different timing patterns for the control signals that govern a memory device.
These patterns define how the external control signals behave in read-access, write-access,
burst read-access, or burst write-access requests. You decide how the external control
signals toggle when the periodic timers reach the maximum programmed value for refresh
operation.
15.1 FEATURES
The following is a list of the memory controller’s main features:
Eight Memory Banks
t 32-bit address decode with mask
t Various block sizes (32K to 4G)
t Byte parity generation/checking
t Write-protection capability
t “Address types” match qualifying memory bank accesses for internal masters
t Timing pattern machine selected according to the type of memory device accessed
t Support for external master access to memory banks
t Synchronous and asynchronous external masters support
General-Purpose Chip-Select Machine
t Compatible with SRAM, EPROM, FEPROM, and peripherals
t Global (boot) chip-select available at system reset
t Boot chip-select support for 8-, 16-, and 32-bit devices
t Two clock accesses to external device
t Four byte write enable (WE[0:3]) signals
t Output enable (OE) signal