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Communication Processor Module
MOTOROLA
MPC823 USER’S MANUAL
16-481
PORTS
COMMUNICATION
16
PROCESSOR
MODULE
The port C lines associated with the CD2 and CTS2 pins have a mode of operation in which
the pin can be internally connected to the serial communication controller but can also
generate interrupts. Port C still detects changes on the CTS2 and CD2 pins and asserts the
corresponding interrupt request, but the serial communication controller simultaneously
uses the CTS2 and/or CD2 pin to automatically control operation. This allows you to fully
implement protocols V.24, X.21, and X.21 bis with the assistance of other general-purpose
I/O lines. To configure a port C pin as a CTS2 or CD2 pin that connects to the serial
communication controller and generates interrupts, follow these steps:
1. Write the corresponding PCPAR bit with a zero.
2. Write the corresponding PCDIR bit with a zero.
3. Write the corresponding PCSO bit with a 1.
4. Set the PCINT bit to find out which edges cause the interrupts.
5. Write the corresponding CIMR bit with a 1 so that interrupts can be sent to the core.
6. The pin value can be read at any time using the PCDAT register.
The DREQ1 and DREQ2 pins in port C can assert an external request to the RISC
microcontroller instead of asserting an interrupt to the core. You can program each pin to
assert an interrupt request when a high-to-low change occurs or any change that as
configured in PCINT.
16.14.9 Port C Registers
You can communicate with the port C using five registers. The port C interrupt control
register (PCINT) indicates how changes on the pin cause interrupts when they are
generated with that pin. The port C special options register (PCSO) indicates whether
certain port C pins can connect to on-chip peripherals and generate an interrupt at the same
time. The remaining port C registers exist on the other ports as well. However, since port C
does not have an open-drain capability, there is no open-drain register.
Note: After connecting the CTS2 or CD2 pins to the serial communication controller,
you must also choose “normal operation” mode in the DIAG field of the GSMR_L
to enable or disable SCC2 transmission and reception with these pins.
Note: Do not program the DREQ1 and DREQ2 pins to assert external requests to the
RISC microcontroller, unless instructed to do so by Motorola as part of a RAM
microcode package. Otherwise, erratic behavior will occur.