參數(shù)資料
型號(hào): MPC603RRX266TC
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 14/31頁(yè)
文件大?。?/td> 0K
描述: IC MPU 32BIT 266MHZ 255-CBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC6xx
處理器類型: 32-位 MPC603e PowerPC
速度: 266MHz
電壓: 2.5V
安裝類型: 表面貼裝
封裝/外殼: 255-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 255-FCCBGA(21x21)
包裝: 托盤(pán)
PID7t-603e Hardware Specifications, Rev. 5
Freescale Semiconductor
21
System Design Information
8.1
PLL Configuration
The 603e PLL is configured by the PLL_CFG[0–3] signals. For a given SYSCLK (bus) frequency, the
PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration
for the PID7t-603e is shown in this table for nominal frequencies.
8.2
PLL Power Supply Filtering
The AVdd power signal is provided on the 603e to provide power to the clock generation phase-locked
loop. To ensure stability of the internal clock, the power supplied to the AVdd input signal should be filtered
Table 12. PLL Configuration
PLL_CFG[0:3]
CPU Frequency in MHz (VCO Frequency in MHz)
Bus-to-Core
Multiplier
Core-to-VCO
Multiplier
Bus
25 MHz
Bus
33.33 MHz
Bus
40 MHz
Bus
50 MHz
Bus
60 MHz
Bus
66.67 MHz
Bus
75 MHz
0100
2x
150
(300)
0101
2x
4x
804
(320)
100
(400)
120
(480)
133
(532)
150
(600)
0110
2.5x
2x
150
(300)
166
(333)
187
(375)
1000
3x
2x
150
(300)
180
(360)
200
(400)
225
(450)
1110
3.5x
2x
175
(350)
210
(420)
233 (466)
263
(525)
1010
4x
2x
160
(320)
200
(400)
240
(480)
267 (533)
300
(600)
0111
4.5x
2x
150
(300)
180
(360)
225
(450)
270
(540)
300 (600)
1011
5x
2x
166
(333)
200
(400)
250
(500)
300
(600)
——
1001
5.5x
2x
183 (366)
220
(440)
275
(550)
———
1101
6x
2x
150
(300)
200
(400)
240
(480)
300
(600)
———
0011
PLL bypass
1111
Clock off
Note:
1. Some PLL configurations may select bus, CPU, or VCO frequencies which are not supported; see Section 4.2.1, “Clock
AC Specifications,” for valid SYSCLK and VCO frequencies.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus
mode is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
3. In clock-off mode, no clocking occurs inside the 603e regardless of the SYSCLK input.
4. 80 MHz operation is not supported for the PBGA package (see Table 7).
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