LOGIC COMMANDS AND REGISTERS If the watchd" />
參數(shù)資料
型號: MM908E621ACDWBR2
廠商: Freescale Semiconductor
文件頁數(shù): 38/60頁
文件大?。?/td> 0K
描述: IC SW QUAD HB/TRPL HISID 54-SOIC
標(biāo)準(zhǔn)包裝: 1,000
應(yīng)用: 自動鏡像控制
核心處理器: HC08
程序存儲器類型: 閃存(16 kB)
控制器系列: 908E
RAM 容量: 512 x 8
接口: SCI,SPI
輸入/輸出數(shù): 12
電源電壓: 9 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 54-BSSOP(0.295",7.50mm 寬)裸露焊盤
包裝: 帶卷 (TR)
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
Analog Integrated Circuit Device Data
Freescale Semiconductor
43
908E621
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
If the watchdog is enabled, it will generate a system reset,
if the timer has reached its end value, or if a watchdog reset
(WDRST) has occurred in the closed window.
The watchdog period can be selected with 2 bits in the
WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period.
Figure 28. Window Watchdog Period
Stop mode
Operations of the watchdog function is halted in stop mode
(counter/oscillator stopped). After wake-up, the watchdog
timer is automatically cleared, in order to give the MCU the
full time to reset the watchdog.
Sleep mode
Operations of the watchdog function is halted in sleep
mode. Because the main voltage regulator asserts an LVR
reset, the Watchdog functionality is disabled, and the WDRE
bit is cleared as soon as sleep mode is entered. To re-enable
this function bit WDRE has to be set after wake-up.
Watchdog Control Register (WDCTL)
WDRE - Watchdog Reset Enable Bit
This read/write (write once) bit activates the watchdog.
The WDRE can only be set and can not be cleared by
software. Reset clears the WDRE bit.
1 = Watchdog enabled
0 = Watchdog disabled
WDP1:0 - Watchdog Period Select Bits
This read/write bit select the clock rate of the Watchdog.
Reset clears the WDP1:0 bits.
WDRST - Watchdog Reset Bit
This write only bit resets the Watchdog. Write a logic [1] to
reset the watchdog timer.
1 = Reset WD and restart timer
0 = no effect
Voltage Regulator
The 908E621 contains a low power, low drop voltage
regulator, to provide internal power and external power for
the MCU. The on-chip regulator consist of two elements, the
main regulator and the low voltage reset circuit.
The VDD regulator accepts an unregulated input supply
and provides a regulated VDD supply to all digital sections of
the device. The output of the regulator is also connected to
the VDD pin to provide the 5.0 V to the microcontroller.
Run mode
During RUN mode the main voltage regulator is on. It will
provide a regulated supply to all digital sections.
STOP mode
During STOP mode, the Stop mode regulator will take care
of suppling a regulated output voltage. The Stop mode
regulator has a limited output current capability.
SLEEP mode
In Sleep mode, the main voltage regulator external, VDD,
is turned off and the LVR circuitry will force the RST_A pin
low.
LOGIC COMMANDS AND REGISTERS
908E621 SERIAL PHERIPHERAL INTERFACE (SPI)
The Serial Peripheral Interface (SPI) creates the
communication link between the MCU and the analog die.
The interface consists of four pins
MOSI - Master Out Slave In (internal pulldown)
MISO - Master In Slave Out
SPSCK - Serial Clock (internal pulldown)
SS - Slave Select (internal pullup)
A complete data transfer via the SPI, consists of 2 bytes.
The master sends address and data, the slave returns
system status and the data of the selected address.
Register Name and Address: WDCTL - $0B
Bit7
6
5
4
3
2
1
Bit0
Read
WDRE
WDP1
WDP0
0
000
0
Write
WDRST
Reset
0
Window closed
no watch dog clear allowed
Window open
for watch dog clear
WD timing x 50%
WD period ( timing selected by Bits WDP1:0)
Table 11. Watchdog Period Selection Bits
WDP1
WDP0
Mode
0
80 ms window watchdog period
0
1
40 ms window watchdog period
1
0
20 ms window watchdog period
1
10 ms window watchdog period
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