參數(shù)資料
型號： MK51DX256ZCLL10
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, LQFP-100
文件頁數(shù)： 40/74頁
文件大?。?/td> 1031K
代理商： MK51DX256ZCLL10
Table 28. 16-bit ADC with PGA characteristics (continued)
Symbol
Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VPP,DIFF
Maximum
differential input
signal swing
where VX = VREFPGA × 0.583
V
SNR
Signal-to-noise
ratio
Gain=1
Gain=64
TBD
83.0
57.5
—
dB
16-bit
differential
mode,
Average=32
THD
Total harmonic
distortion
Gain=1
Gain=64
TBD
89.4
90.0
—
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
SFDR
Spurious free
dynamic range
Gain=1
Gain=64
TBD
90.9
77.0
—
dB
16-bit
differential
mode,
Average=32,
fin=500Hz
ENOB
Effective number
of bits
Gain=1, Average=4
Gain=1, Average=8
Gain=64, Average=4
Gain=64, Average=8
Gain=1, Average=32
Gain=2, Average=32
Gain=4, Average=32
Gain=8, Average=32
Gain=16, Average=32
Gain=32, Average=32
Gain=64, Average=32
TBD
12.3
12.7
8.4
8.7
13.3
13.1
12.5
11.8
11.1
10.2
9.3
—
bits
16-bit
differential
mode,fin=100H
z
SINAD
Signal-to-noise
plus distortion
ratio
See ENOB
6.02 × ENOB + 1.76
dB
1. Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated.
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
function of input common mode voltage (VCM) and the PGA gain.
4. Gain = 2PGAG
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
PGA reference voltage and gain setting.
Peripheral operating requirements and behaviors
K51 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
45
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