參數(shù)資料
型號: MK51DX256ZCLL10
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, LQFP-100
文件頁數(shù): 25/74頁
文件大?。?/td> 1031K
代理商: MK51DX256ZCLL10
Table 16. Oscillator DC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Vpp5
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
VDD
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
0.6
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
V
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any
other devices.
6.3.2.2 Oscillator frequency specifications
Table 17. Oscillator frequency specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
32
40
kHz
fosc_hi_1
Oscillator crystal or resonator frequency — high
frequency mode (low range)
(MCG_C2[RANGE]=01)
3
8
MHz
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
32
MHz
fec_extal
Input clock frequency (external clock mode)
50
MHz
tdc_extal
Input clock duty cycle (external clock mode)
40
50
60
%
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
2, 3
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
250
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
0.6
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
1
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL
2. Proper PC board layout procedures must be followed to achieve specifications.
Peripheral operating requirements and behaviors
K51 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Freescale Semiconductor, Inc.
Preliminary
31
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