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參數(shù)資料
| 型號(hào)： | MK2058-01SILF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 164K |
| 代理商： | MK2058-01SILF |
Communications Clock Jitter Attenuator
MDS 2058-01 C
5
Revision 050803
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
MK2058-01
A “normalized” PLL loop bandwidth may be calculated
as follows:
The “normalized” bandwidth equation above does not
take into account the effects of damping factor or the
second pole. However, it does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
Where:
RS = Value of resistor in loop filter (Ohms)
ICP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
CS = Value of capacitor C1 in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C1 and C2 in the loop
filter:
Charge Pump Current Table
Special considerations must be made in choosing loop
www.icst.com.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
W trace (a
commonly used trace impedance), place a 33
W resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
W. (The optional series termination resistor
is not shown in the External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2058-01 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK2058-01 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Recommended Power Supply Connection
for Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as CL in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
RSET
Charge Pump Current
(ICP)
1.4 M
W
10
mA
680 k
W
20
mA
540 k
W
25
mA
120 k
W
100
mA
NBW
RS ICP
575
N
---------------------------------------
=
Damping Factor
RS
625
I
CP
CS
N
-----------------------------------------
=
CP
CS
20
------
=
C onnection to 3.3V
Pow er Plane
Ferrite
Bead
B ulk D ecoupling C apac itor
(such as 1
F Tantalum)
V DD P in
0.01
F Decoupling Capacitors
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2058-01SILFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 COMMUNICATIONS CLOCK JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK205801SITR | 制造商:Integrated Device Technology Inc 功能描述: |
| MK2058-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2059-01 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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