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參數(shù)資料
| 型號(hào)： | MK2058-01SILF |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 164K |
| 代理商： | MK2058-01SILF |
Communications Clock Jitter Attenuator
MDS 2058-01 C
3
Revision 050803
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ●
www.icst.com
MK2058-01
Functional Description
The MK2058-01 is a clock generator IC that generates
an output clock directly from an internal VCXO circuit
which works in conjunction with an external quartz
crystal. The VCXO is controlled by an internal PLL
(Phase Locked Loop) circuit, enabling the device to
perform clock regeneration from an input reference
clock. The MK2058-01 is configured to provide an
output clock that is the same frequency as the input
clock. There are 12 selectable input / output frequency
ranges, each of which is a submultiple of the supported
quartz crystal frequency range. Please refer to the
Output Clock Selection Table on Page 2.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the MK2058-01 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low frequency
reference clock.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
Application Information
Input / Output Frequency Configuration
The MK2058-01 is configured to generate an output
frequency that is equal to the input reference
frequency. Clock frequencies that are supported are
those which fall into the ranges listed in the Output
Clock Selection Table on Page 2. Input bits SEL2:0 are
set according to this table, as is the external crystal
frequency. The nominal (center) frequency of the
external crystal will be an integer multiple of the input /
output clock as specified. Please refer to the Quartz
Crystal section on this page regarding external crystal
requirements.
Input Mux
The Input Mux serves to select between two alternate
input reference clocks. Upon reselection of the input
clock, clock glitches on the output clock will not be
generated due to the “fly-wheel” effect of the VCXO
(the quartz crystal is a high-Q tuned circuit). When the
input clocks are not phase aligned, the phase of the
output clock will change to reflect the phase of the
newly selected input at a controlled phase slope (rate
of phase change) as influenced by the PLL loop
characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the MK2058-01. Failure to do so may result in
reduced frequency pullability range, inability of the loop
to lock, or excessive output phase jitter.
The MK2058-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The MK2058-01 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the MK2058-01 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2058-01 and the
crystal.
A complete description of the recommended crystal
parameters is in application note MAN05.
A list of approved crystals is located on the ICST web
site (www.icst.com).
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The MK2058-01 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2058-01SILFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 COMMUNICATIONS CLOCK JITTER ATTENUATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| MK205801SITR | 制造商:Integrated Device Technology Inc 功能描述: |
| MK2058-01SITR | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2059-01 | 制造商:ICS 制造商全稱:ICS 功能描述:VCXO-Based Frame Clock Frequency Translator |
| MK2059-01SI | 功能描述:IC VCXO CLK JITTER ATTEN 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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