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參數(shù)資料
| 型號(hào)： | MK2049-35SI |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 112K |
| 代理商： | MK2049-35SI |
MK2049-35
3.3 V Communications Clock PLL
MDS 2049-35 B
6
Revision 081401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
Loop Filter Components
CAP2
CAP1
5.6 nF
Crystal Operation
Figure 3. Loop Filter Component Values
(Typical component values are shown. Contact the ICS applications department at
(408)297-1201 for the recommended values for your application)
The MK2049 operates by phase locking the input signal to a VCXO which consists of the special recommended
crystal and the integrated VCXO oscillator circuit on the MK2049. To achieve the best performance and reliability, the
layout guidelines shown on the next page must be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The
MK2049 has variable load capacitors on-chip which “pull”, or change the frequency of the crystal. External stray
capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the layout should
use short traces between the MK2049 and the crystal.
For the VCXO to operate correctly, a crystal properly specified and matched to the MK2049-35 must be used. For
more information, including a list of recommended crystals, refer to the application note MAN05.
The external loop filter should be connected between CAP1 and CAP2 as shown in Figure 3 below, and as close to
the chip as possible. High quality ceramic capacitors are recommended. DO NOT use any type of polarized or
electrolytic capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Another alternative is the Panasonic
PPS polymer dielectric series; their part number for the 0.1 F cap is ECHU1C104JB5. Avoid high-K dielectrics like
Z5U and X7R; these and other ceramics which have piezolectric properties allow mechanical vibration in the system
to increase the output jitter because the mechanical energy is converted directly to voltage noise on the VCO input.
The MK2049-35 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.01F must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17), and
33
series terminating resistors should be used on clock outputs with traces longer than 1 inch (assuming 50
traces). The selection of additional external components is described in the following sections.
EXTERNAL COMPONENT SELECTION
470 k
0.1 F
相關(guān)PDF資料 |
PDF描述 |
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| MK2049-44SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45ASITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SILFTR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2058-01SILF | OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-36SILF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-36SILFTR | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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