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參數(shù)資料
| 型號： | MK2049-35SI |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 49.152 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.300 INCH, SOIC-20 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 112K |
| 代理商： | MK2049-35SI |
MK2049-35
3.3 V Communications Clock PLL
MDS 2049-35 B
5
Revision 081401
Integrated Circuit Systems, Inc. 525 Race Street San Jose CA 95126 (408)295-9800tel www.icst.com
OPERATING MODES
The MK2049-35 has two operating modes: External and Buffer. Although both modes use an input clock to
generate various output clocks, there are important differences in their input and crystal requirements.
External Mode
The MK2049-35 accepts an external 8 kHz clock and will produce a number of common communication clock
frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10
ns is acceptable.
Buffer Mode
Unlike the other mode that accepts only a single specified input frequency, Buffer Mode will accept a wider range of
input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also provide the option of getting x1,
x2, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock,
generating low-jitter 27 MHz and 54 MHz outputs.
FREQUENCY LOCKING TO THE INPUT
In all modes, the output clocks are frequency-locked to the input. The output will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by
up to 60 ppm and still have the output clock remain frequency-locked.
相關(guān)PDF資料 |
PDF描述 |
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| MK2049-44SI | 51.84 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45ASITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SITR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2049-45SILFTR | 125 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| MK2058-01SILF | OTHER CLOCK GENERATOR, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK2049-35SITR | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3 V Communications Clock PLL |
| MK2049-36SI | 功能描述:IC VCXO PLL CLK SYNTH 20-SOIC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK2049-36SILF | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK2049-36SILFTR | 功能描述:時鐘合成器/抖動清除器 3.3 VOLT COMMUNICA. CLOCK VCXO PLL RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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