參數(shù)資料
型號： MICRF405YML TR
廠商： Micrel Inc
文件頁數(shù)： 37/46頁
文件大?。?/td> 649K
描述： TRANSMITTER ASK/FSK 24-MLF
標(biāo)準(zhǔn)包裝： 1
頻率： 290MHz ~ 980MHz
應(yīng)用： ISM
調(diào)制或協(xié)議： ASK，F(xiàn)SK
數(shù)據(jù)傳輸率 - 最大： 200 kbps
功率 - 輸出： 10dBm
電流 - 傳輸： 18mA
數(shù)據(jù)接口： PCB，表面貼裝
天線連接器： PCB，表面貼裝
電源電壓： 2.2 V ~ 3.6 V
工作溫度： -40°C ~ 125°C
封裝/外殼： 24-VFQFN 裸露焊盤，24-MLF?
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 571 (CN2011-ZH PDF)
其它名稱： 576-1965-6
Micrel
MICRF405
 
 
 
 
April 2006 
37
M9999-041906
 (408) 955-1690
 
 
LDO_by    LDO_EN1    LDO_EN0     Comments
X
0
0
LDOs turned off, power applied to AVDD, DVDD, RFVDD, min/max is 2.0/2.5 V, and
to VDD pin 11 and 1, min/max is 2.0/3.6V.
1
X
X
LDOs bypassed, power applied to the VDD pin1 and VDD pin11, min/max is 2.0/2.5 V
0
0
1
PA LDO turned on, power applied to VDD pin1 and 11, min/max is 2.0/3.6V, and to
AVDD and DVDD, min/max is 2.0/2.5V
0
1
0
PA and AVDD LDO turned on, power applied to the VDD pin1 and 11, min/max is
2.0/3.6V, and to DVDD, min/max is 2.0/2.5V
0
1
1
PA, AVDD and DIG LDO turned on, power applied to the VDD pin1 and VDD pin 11,
min/max is 2.0/3.6V
Table 30. Low DropOut Voltage Regulator.
 
PA_LDc_en Comments
0
PA is only controlled by Mode1 and Mode and PA0-2, PA on in transmit mode (Mode[1:0]=3 and PA[2:0]>0)
1
In transmit mode, PA is turned on by Lock Detect (LD=1 -> PA on). PA is turned off by load pulse or when
using openloop modulation and setting the DATAIN pin in tri-state. PA will be turned on again once LD goes
high again. LD_en must be set to 1.
Table 31. Lock Detect Controlled PA.
 
MOD_LDc_en    Comments
0
Modulation starts once frame length is written into data byte.
1
Modulation starts once frame length is written into data byte and PA is turned on and LD is high.
Table 32. Lock Detect Controlled Start of Modulation (only for BIT_IO_en=0).
 
PA_FEc_en     Comments
0
PA is turned off by Mode1 and Mode0 or PA0-2 and PA_LDc_en=0
1
PA is turned off immediately after the frame is transmitted.
Table 33. Frameend Controlled PA.
 
LD_en
State
Comments
0
LD off
Output is 0 volt, or test signals specified by OUTS[2:0]
1
LD on
LD pin high indicate that the PLL is locked
Table 34. Lock Detector.
 
SyncID_Len1     SyncID_Len0
Comments
0
0
SyncID length is 1 byte. SyncID0 is sent
0
1
SyncID length is 2 bytes. SyncID0 and SyncID1 is sent
1
0
SyncID length is 3 bytes. SyncID0, SyncID1 and SyncID2 is sent
1
1
SyncID length is 4 bytes. SyncID0, SyncID1, SyncID2 and SyncID3 is sent.
Table 35. SyncID Field Length.
 
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