參數(shù)資料
型號： MCZ33780EGR2
廠商： Freescale Semiconductor
文件頁數(shù)： 15/37頁
文件大?。?/td> 0K
描述： IC MASTER DUAL DBUS DIFF 16-SOIC
標(biāo)準(zhǔn)包裝： 1,000
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 16-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC W
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
22
Freescale Semiconductor
33780
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
Figure 18. Logic Block Diagram
LOGIC BLOCK DIAGRAM DESCRIPTION
Figure 18, Logic Block Diagram, shows a block diagram of
the major logic blocks in the IC.
SPI
The SPI is a standard serial peripheral interface. This
interface provides two-way communications between the IC
and an MCU. The MCU can write to registers that control the
operation of the IC and read back the conditions in the IC
using the SPI. It can also write data to be sent out on the
DBUS and read data that was returned on the DBUS. The
register pointer and bit pointer are used to control which
registers and bits are being written to and read from using the
SPI. Its operation is described in detail in the section entitled
REGISTERS
The register set consists of control, status, transmit, and
receive types. They are written and read using the SPI
interface and are affected by events in the IC. Detailed
descriptions of their operation and use can be found
throughout later sections of this data sheet.
INTERRUPT
The Interrupt block controls the INT output pin. The main
purpose of the Interrupt is to quickly inform the MCU when
data has been received via the DBUS or when the DBUS
transmit buffer is empty. The INT output can only drive the
level on the pin low. The internal pull-up current or an external
resistor to VCC is used to pull this pin high. This is done so
that other ICs can be connected to the interrupt pin on the
Channel 0
Clock Select and Divider
CLK_VCO1
CLK
CLK_VCO0
Interrupt
INT
status regs
control regs
enable regs
poly regs
seed regs
length regs
SS ctrl regs
SS offset regs
SS Up/Dwn regs
register pointer
bit pointer
SPI XFER
RST
MISO
SCLK
CS
MOSI
RX Buffer
TX Buffer
RX FIFO
TX FIFO
C
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RX0 Data
RX0 Status
TX0 Data
TX0 Status
RX1 Data
RX1 Status
TX1Data
TX1 Status
CH0
CH1
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B
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Channel 1
Clock Select and Divider
CLK
Bit Clock 0
Bit Clock 1
CH0 Enable
CH1 Enable
RX Buffer
TX Buffer
RX FIFO
TX FIFO
C
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SPI & Registers
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MCZ33781EKR2 功能描述:輸入/輸出控制器接口集成電路 DBUS2 MASTER STND RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
MCZ33784EF 功能描述:加速計 - 板上安裝 DBUS2 SENSOR INTERFACE RoHS:否 制造商:Murata 傳感軸:Double 加速:12 g 靈敏度: 封裝 / 箱體: 輸出類型:Analog 數(shù)字輸出 - 位數(shù):11 bit 電源電壓-最大:5.25 V 電源電壓-最小:4.75 V 電源電流:4 mA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C
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