參數(shù)資料
型號: MCZ33780EGR2
廠商: Freescale Semiconductor
文件頁數(shù): 10/37頁
文件大?。?/td> 0K
描述: IC MASTER DUAL DBUS DIFF 16-SOIC
標準包裝: 1,000
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC W
包裝: 帶卷 (TR)
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
18
Freescale Semiconductor
33780
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
automatically to a slow acquisition mode (180.224 ms per
update cycle, based on 4.0 MHz clock).
SPREADER LOGIC
The Spreader Logic contains a pseudo-random binary
sequence (PRBS) generator and time compensation
circuitry. The PRBS can generate maximal length sequences
of 6, 7, 11, and 15 bits. Maximal length means there is no
repeat of the sequence until 2n counts have been reached,
where n is the selected length.
A special feature of the Spreader Logic is that the bit
periods are chosen in a way to keep the length of the frame
constant, provided that the total number of bits is even. This
is useful if the time between samples made by the slaves
must be kept relatively constant. Without this feature, the time
from sample-to-sample would vary randomly.
The DEV1 and DEV0 bits in the DnSSCTRL register
control whether the deviation is enabled or disabled.
The Spreader Logic is synchronized to only change the
value of the digital word to the Spreader DAC at the
beginning of a DBUS bit. When spreading is enabled, these
changes will occur once per DBUS bit-time.
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