參數(shù)資料
型號: MCZ33742SEGR2
廠商: 飛思卡爾半導體(中國)有限公司
元件分類: CAN
英文描述: System Basis Chip (SBC) with Enhanced High-Speed CAN Transceiver
中文描述: 系統(tǒng)基礎(chǔ)芯片的增強型(SBC)的高速CAN收發(fā)器
文件頁數(shù): 5/65頁
文件大?。?/td> 1158K
代理商: MCZ33742SEGR2
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
33742
PIN CONNECTIONS
Figure 4. 33742
48-Pin Connections
Table 3. 33742 48-Pin Definitions
A functional description of each pin can be found in the
Functional Pin description
section beginning on page
22
.
Pin
Pin Name
Formal Name
Definition
1, 12-16,
21-25,
36-40,
45-48
NC
No Connect
No connection.
2
SCLK
Serial Data Clock
Clock input pin for the Serial Peripheral Interface (SPI).
3
MISO
Master In Slave Out
SPI data sent to the MCU by the 33742. When CS is HIGH, the pin is in the high-
impedance state.
4
MOSI
Master Out Slave In
SPI data received by the 33742.
5
CS
Chip Select
(Active LOW)
The CS input pin is used with the SPI bus to select the 33742. When the CS is asserted
LOW, the 33742 is the selected device of the SPI bus.
6
WDOG
Watchdog Output
(Active LOW)
The WDOG output pin is asserted LOW if the software watchdog is not correctly
triggered.
7
RXD
Receive Data
CAN bus receive data output pin.
8
TXD
Transmit Data
CAN bus transmit data input pin.
9
VDD
Voltage Digital Drain
5.0 V regulator output pin. Supply pin for the MCU.
10
RST
Reset Output
(Active LOW)
This is the device reset output pin whose main function is to reset the MCU. This pin has
an internal pullup current source to VDD.
11
INT
Interrupt Output
(Active LOW)
This output is asserted LOW when an enabled interrupt condition occurs. The output is
a push-pull structure.
17-20
41-44
GND
Ground
These device ground pins are internally connected to the package lead frame to provide
a 33742-to-PCB thermal path.
G
G
G
SCLK
MISO
MOSI
CS
4
5
6
7
8
9
10
11
12
2
3
32
31
30
29
28
27
26
25
1
1
N
1
N
1
N
36
35
34
33
RXD
TXD
1
G
1
G
3
3
4
4
4
4
1
G
2
G
2
N
2
N
2
N
4
4
4
4
4
G
L3
L2
L1
L0
HS
VSUP
NC
N
N
VDD
RST
1
N
3
V2 CTRL
V2
NC
CANH
CANL
NC
N
N
N
N
N
WDOG
INT
NC
N
N
2
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