I2C BUS DATA REQUIRE" />
參數(shù)資料
型號： MCP47DA1T-A1E/OT
廠商： Microchip Technology
文件頁數(shù)： 54/54頁
文件大?。?/td> 0K
描述： IC DGTL POT 30K 1CH SOT-23-6
標(biāo)準(zhǔn)包裝： 1
接片： 65
電阻（歐姆）： 30k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 150 ppm/°C
存儲器類型： 易失
接口： I²C
電源電壓： 1.8 V ~ 5.5 V，2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： SOT-23-6
供應(yīng)商設(shè)備封裝： SOT-23-6
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： MCP47DA1T-A1E/OTDKR
2012 Microchip Technology Inc.
DS25118C-page 9
MCP47DA1
TABLE 1-2:
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40
C TA +125C (Extended)
Operating Voltage VDD range is described in “AC/DC characteristics”
Parame-
ter No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4000
—
ns
1.8V-5.5V
400 kHz mode
600
—
ns
2.7V-5.5V
101
TLOW
Clock low time
100 kHz mode
4700
—
ns
1.8V-5.5V
400 kHz mode
1300
—
ns
2.7V-5.5V
102A
(5)
TRSCL
SCL rise time
100 kHz mode
—
1000
ns
Cb is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1Cb
300
ns
102B
(5)
TRSDA
SDA rise time
100 kHz mode
—
1000
ns
Cb is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1Cb
300
ns
103A
(5)
TFSCL
SCL fall time
100 kHz mode
—
300
ns
Cb is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1Cb
40
ns
103B
(5)
TFSDA
SDA fall time
100 kHz mode
—
300
ns
Cb is specified to be from
10 to 400 pF
400 kHz mode
20 + 0.1Cb
(5)
300
ns
106
THD:DAT
Data input hold
time
100 kHz mode
0
—
ns
1.8V-5.5V (Note 6)
400 kHz mode
0
—
ns
2.7V-5.5V (Note 6)
107
TSU:DAT
Data input
setup time
100 kHz mode
250
—
ns
Note 5
400 kHz mode
100
—
ns
109
TAA
Output valid
from clock
100 kHz mode
—
3450
ns
Note 5
400 kHz mode
—
900
ns
110
TBUF
Bus free time
100 kHz mode
4700
—
ns
Time the bus must be free
before a new transmission
can start
400 kHz mode
1300
—
ns
TSP
Input filter spike
suppression
(SDA and SCL)
100 kHz mode
—
50
ns
Philips spec. states N.A.
400 kHz mode
—
50
ns
Note 1:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2:
A fast-mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the
requirement tsu; DAT
250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line.
TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3:
The MCP47DA1 device must provide a data hold time to bridge the undefined part between VIH and VIL of
the falling edge of the SCL signal. This specification is not a part of the I2C specification, but must be
tested in order to ensure that the output data will meet the setup and hold specifications for the receiving
device.
4:
Use Cb in pF for the calculations.
5:
Not tested.
6:
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a START or STOP condition.
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