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| 型號： | MCP47DA1T-A1E/OT |
| 廠商： | Microchip Technology |
| 文件頁數： | 16/54頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 30K 1CH SOT-23-6 |
| 標準包裝： | 1 |
| 接片： | 65 |
| 電阻（歐姆）： | 30k |
| 電路數： | 1 |
| 溫度系數： | 標準值 150 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C |
| 電源電壓： | 1.8 V ~ 5.5 V，2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 其它名稱： | MCP47DA1T-A1E/OTDKR |
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Micrel, Inc.
KSZ8041NL/RNL
September 2010
23
M9999-090910-1.4
MII Management (MIIM) Interface
The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the
KSZ8041NL/RNL. An external device with MIIM capability is used to read the PHY status and/or configure the PHY
settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
A specific protocol that operates across the aforementioned physical connection that allows a external controller
to communicate with one or more PHY devices. Each KSZ8041NL/RNL device is assigned a unique PHY address
between 1 and 7 by its PHYAD[2:0] strapping pins. Also, every KSZ8041NL/RNL device supports the broadcast
PHY address 0, as defined per the IEEE 802.3 Specification, which can be used to read/write to a single
KSZ8041NL/RNL device, or write to multiple KSZ8041NL/RNL devices simultaneously.
A set of 16-bit MDIO registers. Register [0:6] are required, and their functions are defined per the IEEE 802.3
Specification. The additional registers are provided for expanded functionality.
The Table 1 shows the MII Management frame format for the KSZ8041NL/RNL.
Preamble
Start of
Frame
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
TA
Data
Bits [15:0]
Idle
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 1. MII Management Frame Format
Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits, and
are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading register
1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
MII Data Interface (KSZ8041NL only)
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
Supports 10Mbps and 100Mbps data rates.
Uses a 25MHz reference clock, sourced by the PHY.
Provides independent 4-bit wide (nibble) transmit and receive data paths.
Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041NL is configured to MII mode after it is power-up or reset with the following:
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting).
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