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| 型號： | MCP2510T-E/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 40/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CAN CONTROLLER W/SPI 18-SOIC |
| 標準包裝： | 1,100 |
| 控制器類型： | CAN 接口 |
| 接口： | SPI |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 10mA |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 18-SOIC |
| 包裝： | 帶卷 (TR) |
| 配用： | DV251001-ND - KIT DEVELOPMENT CAN MCP2510 |
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2007 Microchip Technology Inc.
DS21291F-page 45
MCP2510
7.0
INTERRUPTS
The device has eight sources of interrupts. The CAN-
INTE register contains the individual interrupt enable
bits for each interrupt source. The CANINTF register
contains the corresponding interrupt flag bit for each
interrupt source. When an interrupt occurs the INT pin
is driven low by the MCP2510 and will remain low until
the Interrupt is cleared by the MCU. An Interrupt can
not be cleared if the respective condition still prevails.
It is recommended that the bit modify command be
used to reset flag bits in the CANINTF register rather
than normal write operations. This is to prevent unin-
tentionally changing a flag that changes during the
write command, potentially causing an interrupt to be
missed.
It should be noted that the CANINTF flags are read/
write and an Interrupt can be generated by the MCU
setting any of these bits, provided the associated CAN-
INTE bit is also set.
7.1
Interrupt Code Bits
The source of a pending interrupt is indicated in the
CANSTAT.ICOD (interrupt code) bits as indicated in
Register 9-2. In the event that multiple interrupts occur,
the INT will remain low until all interrupts have been
reset by the MCU, and the CANSTAT.ICOD bits will
reflect the code for the highest priority interrupt that is
currently pending. Interrupts are internally prioritized
such that the lower the ICOD value the higher the inter-
rupt priority. Once the highest priority interrupt condi-
tion has been cleared, the code for the next highest
priority interrupt that is pending (if any) will be reflected
by the ICOD bits (see Table 7-1). Note that only those
interrupt sources that have their associated CANINTE
enable bit set will be reflected in the ICOD bits.
TABLE 7-1:
ICOD<2:0> DECODE
7.2
Transmit Interrupt
When the Transmit Interrupt is enabled (CAN-
INTE.TXNIE = 1) an Interrupt will be generated on the
INT pin when the associated transmit buffer becomes
empty and is ready to be loaded with a new message.
The CANINTF.TXNIF bit will be set to indicate the
source of the interrupt. The interrupt is cleared by the
MCU resetting the TXNIF bit to a ‘0’.
7.3
Receive Interrupt
When
the
Receive
Interrupt
is
enabled
(CAN-
INTE.RXNIE = 1) an interrupt will be generated on the
INT pin when a message has been successfully
received and loaded into the associated receive buffer.
This interrupt is activated immediately after receiving
the EOF field. The CANINTF.RXNIF bit will be set to
indicate the source of the interrupt. The interrupt is
cleared by the MCU resetting the RXNIF bit to a ‘0’.
7.4
Message Error Interrupt
When an error occurs during transmission or reception
of
a
message
the
message
error
flag
(CAN-
INTF.MERRF) will be set and, if the CANINTE.MERRE
bit is set, an interrupt will be generated on the INT pin.
This is intended to be used to facilitate baud rate deter-
mination when used in conjunction with listen-only
mode.
7.5
Bus Activity Wakeup Interrupt
When the MCP2510 is in sleep mode and the bus activ-
ity wakeup interrupt is enabled (CANINTE.WAKIE = 1),
an interrupt will be generated on the INT pin, and the
CANINTF.WAKIF bit will be set when activity is
detected on the CAN bus. This interrupt causes the
MCP2510 to exit sleep mode. The interrupt is reset by
the MCU clearing the WAKIF bit.
ICOD<2:0>
Boolean Expression
000
ERRWAKTX0TX1TX2RX0RX1
001
ERR
010
ERRWAK
011
ERRWAKTX0
100
ERRWAKTX0TX1
101
ERRWAKTX0TX1TX2
110
ERRWAKTX0TX1TX2RX0
111
ERRWAKTX0TX1TX2RX0RX1
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