參數(shù)資料
型號： MCIMX356AVM5B
廠商： Freescale Semiconductor
文件頁數(shù)： 4/147頁
文件大?。?/td> 0K
描述： IC MPU I.MX35 400MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： i.MX35
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.33 V ~ 1.47 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 400-LFBGA
包裝： 托盤
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
101
4.9.17
Parallel ATA Module AC Electrical Specifications
The parallel ATA module can work on PIO/multiword DMA/ultra-DMA transfer modes (not available for
the MCIMX351). Each transfer mode has a different data transfer rate, Ultra DMA mode 4 data transfer
rate is up to 100 MBps.
The parallel ATA module interface consists of a total of 29 pins. Some pins have different functions in
different transfer modes. There are various requirements for timing relationships among the function pins,
in compliance with the ATA/ATAPI-6 specification, and these requirements are configurable by the ATA
module registers.
4.9.17.1
General Timing Requirements
Table 67 and Figure 74 define the AC characteristics of the interface signals on all data transfer modes.
Figure 74. ATA Interface Signals Timing Diagram
4.9.17.2
ATA Electrical Specifications (ATA Bus, Bus Buffers)
This section discusses ATA parameters. For a detailed description, refer to the ATA-6 specification.
Level shifters are required for 3.3-V or 5.0-V compatibility on the ATA interface.
The use of bus buffers introduces delays on the bus and introduces skew between signal lines. These factors
make it difficult to operate the bus at the highest speed (UDMA-5) when bus buffers are used. Use of bus
buffers is not recommended if fast UDMA mode is required.
The ATA specification imposes a slew rate limit on the ATA bus. According to this limit, any signal driven
on the bus should have a slew rate between 0.4 and 1.2 V/ns with a 40 pF load. Few vendors of bus buffers
specify the slew rate of the outgoing signals.
When bus buffers are used the ata_data bus buffer is bidirectional, and uses the direction control signal
ata_buffer_en. When ata_buffer_en is asserted, the bus should drive from host to device. When
Table 67. AC Characteristics of All Interface Signals
ID
Parameter
Symbol
Min.
Max.
Unit
SI1
Rising edge slew rate for any signal on the ATA interface1
1 SRISE and SFALL meet this requirement when measured at the sender’s connector from 10–90% of full signal amplitude with
all capacitive loads from 15 pF through 40 pF, where all signals have the same capacitive load value.
Srise
—1.25
V/ns
SI2
Falling edge slew rate for any signal on the ATA interface1
Sfall
—1.25
V/ns
SI3
Host interface signal capacitance at the host connector
Chost
—20
pF
ATA Interface Signals
SI1
SI2
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