參數(shù)資料
型號： MCIMX356AVM5B
廠商： Freescale Semiconductor
文件頁數(shù)： 104/147頁
文件大?。?/td> 0K
描述： IC MPU I.MX35 400MAPBGA
標(biāo)準(zhǔn)包裝： 90
系列： i.MX35
核心處理器： ARM11
芯體尺寸： 32-位
速度： 532MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，I²C，MMC，SPI，SSI，UART/USART，USB OTG
外圍設(shè)備： DMA，I²S，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 96
程序存儲器類型： ROMless
RAM 容量： 128K x 8
電壓 - 電源 (Vcc/Vdd)： 1.33 V ~ 1.47 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 400-LFBGA
包裝： 托盤
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
6
The i.MX35 core is intended to operate at a maximum frequency of 532 MHz to support the required
multimedia use cases. Furthermore, an image processing unit (IPU) is integrated into the AP domain to
offload the ARM11 core from performing functions such as color space conversion, image rotation and
scaling, graphics overlay, and pre- and post-processing.
The functionality of AP Domain peripherals includes the user interface; the connectivity, display, security,
and memory interfaces; and 128 Kbytes of multipurpose SRAM.
2.2
Shared Domain Overview
The shared domain is composed of the shared peripherals, a smart DMA engine (SDMA) and a number of
miscellaneous modules. For maximum flexibility, some peripherals are directly accessible by the SDMA
engine.
The i.MX35 has a hierarchical memory architecture including L1 caches and a unified L2 cache. This
reduces the bandwidth demands for the external bus and external memory. The external memory
subsystem supports a flexible external memory system, including support for SDRAM (SDR, DDR2 and
mobile DDR) and NAND Flash.
2.3
Advanced Power Management Overview
To address the continuing need to reduce power consumption, the following techniques are incorporated
in the i.MX35:
Clock gating
Power gating
Power-optimized synthesis
Well biasing
The insertion of gating into the clock paths allows unused portions of the chip to be disabled. Because
static CMOS logic consumes only leakage power, significant power savings can be realized.
“Well biasing” is applying a voltage that is greater than VDD to the nwells, and one that is lower than VSS
to the pwells. The effect of applying this well back bias voltage reduces the subthreshold channel leakage.
For the 90-nm digital process, it is estimated that the subthreshold leakage is reduced by a factor of ten
over the nominal leakage. Additionally, the supply voltage for internal logic can be reduced from 1.4 V to
1.22 V.
2.4
ARM11 Microprocessor Core
The CPU of the i.MX35 is the ARM1136JF-S core, based on the ARM v6 architecture. This core supports
the ARM Thumb instruction sets, features Jazelle technology (which enables direct execution of Java
byte codes) and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit
registers.
The ARM1136JF-S processor core features are as follows:
Integer unit with integral EmbeddedICE logic
Eight-stage pipeline
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