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參數(shù)資料
| 型號(hào)： | MCIMX31VMN5CR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 532 MHz, MICROPROCESSOR, PBGA473 |
| 封裝： | 19 X 19 MM, 0.80 MM PITCH, ROHS COMPLIANT, MAPBGA-473 |
| 文件頁數(shù)： | 36/122頁 |
| 文件大小： | 1418K |
| 代理商： | MCIMX31VMN5CR2 |
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MCIMX31/MCIMX31L Technical Data, Rev. 4.1
20
Freescale Semiconductor
Electrical Characteristics
Figure 2. Power-Up Sequence for Silicon Revisions 1.2 and Previous
4.2.1.1
Power-Up Sequence for Silicon Revision 2
Silicon revision 2.0 offers two options for power-up sequencing. Option 1 is backwards compatible with
silicon revision 1.2 and earlier versions of the IC. It should be noted that using option 1 on silicon Rev. 2.0
introduces a slight increase in current drain on IOQVDD when IOQVDD is raised before NVCC21. The
expected resulting increase is in the range of 3 mA to 5 mA, which does not pose a risk to the IC.
Option 2 is an alternative power-up sequence that allows the powering up of NVCC2, NVCC21, NVCC22
with IOQVDD, NVCC1, and NVCC3-10 without producing a current drain increase on IOQVDD.
These two power-up options on the 2.0 silicon allow the user to select the optimum power-up sequence for
their application.
Release POR
QVCC, QVCC1, QVCC4
IOQVDD, NVCC1, NVCC3–10
FVCC, MVCC,
SVCC, UVCC
NVCC2, NVCC21, NVCC22
FUSE_VDD
Hold POR Asserted
Notes:
1
The board design must guarantee that supplies reach 90% level before transition
to the next state, using Power Management IC or other means.
2
The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD
has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions.
3
It is allowable for FVCC, MVCC, SVCC, and UVCC to be up after FUSE_VDD.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
i.MX31
Product
Family
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