
Chip Select Module
MCF5271 Reference Manual, Rev. 2
16-4
Freescale Semiconductor
Table 16-2 shows the type of access as a function of match in the CSARs and DACRs.
16.3.1.1 8-, 16-, and 32-Bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See
Section 16.4.1.3 for
more information.
Figure 16-1 shows the correspondence between the data bus and the external
byte strobe control lines (BS[3:0]). Note that all byte lanes are driven, although the state of unused
byte lanes is undefined.
Figure 16-1. Connections for External Memory Port Sizes
16.3.2 Enhanced Wait State Operation
The chip-select logic has been enhanced to add the notion of secondary wait-state counter values
to be used after the initial wait-state value (where the existing wait state field becomes the initial
access wait state) is applied to the first access. Two fields in the Chip-Select Control Registers
Table 16-2. Accesses by Matches in CSARs and DACRs
Number of CSCR Matches
Number of DACR Matches
Type of Access
00
External
1
0
Defined by CSAR
Multiple
0
External, burst-inhibited, 32-bit
0
1
Defined by DACRs
1
Undefined
Multiple
1
Undefined
0
Multiple
Undefined
1
Multiple
Undefined
Multiple
Undefined
Byte 0
8-bit port
16-bit port
32-bit port
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
Byte 0
Byte 1
Byte 2
Byte 3
D[31:24]
D[23:16]
D[15:8]
D[7:0]
External
memory
data bus
BS3
BS2
BS1
BS0
Driven, undefined