參數(shù)資料
型號(hào)： MCF52223CVM66J
廠商： Freescale Semiconductor
文件頁數(shù)： 18/55頁
文件大小： 0K
描述： IC MCU 32BIT W/USB 81MAPBGA
標(biāo)準(zhǔn)包裝： 240
系列： MCF5222x
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 66MHz
連通性： I²C，SPI，UART/USART，USB OTG
外圍設(shè)備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲(chǔ)器容量： 256KB（256K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 81-LBGA
包裝： 托盤
MCF52223 ColdFire Microcontroller, Rev. 3
Family Configurations
Freescale Semiconductor
25
1.16
EzPort Signal Descriptions
Table 18 contains a list of EzPort external signals.
Development Serial
Input
DSI
Development Serial Input - Internally synchronized input that provides
data input for the serial communication port to the debug module, after
the DSCLK has been seen as high (logic 1).
I
Development Serial
Output
DSO
Development Serial Output - Provides serial output communication for
debug module responses. DSO is registered internally. The output is
delayed from the validation of DSCLK high.
O
Debug Data
DDATA[3:0]
Display captured processor data and breakpoint status. The CLKOUT
signal can be used by the development system to know when to
sample DDATA[3:0].
O
Processor Status Clock
PSTCLK
Processor Status Clock - Delayed version of the processor clock. Its
rising edge appears in the center of valid PST and DDATA output.
PSTCLK indicates when the development system should sample PST
and DDATA values.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and
PST and DDATA outputs from toggling without disabling triggers.
Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with
the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC,
0xD, or 0xF) occurs during system reset exception processing.
O
Processor Status
Outputs
PST[3:0]
Indicate core status. Debug mode timing is synchronous with the
processor clock; status is unrelated to the current bus transfer. The
CLKOUT signal can be used by the development system to know
when to sample PST[3:0].
O
All Processor Status
Outputs
ALLPST
Logical AND of PST[3:0]. The CLKOUT signal can be used by the
development system to know when to sample ALLPST.
O
Table 18. EzPort Signal Descriptions
Signal Name
Abbreviation
Function
I/O
EzPort Clock
EZPCK
Shift clock for EzPort transfers.
I
EzPort Chip Select
EZPCS
Chip select for signalling the start and end of
serial transfers.
I
EzPort Serial Data In
EZPD
EZPD is sampled on the rising edge of
EZPCK.
I
EzPort Serial Data Out
EZPQ
EZPQ transitions on the falling edge of
EZPCK.
O
Table 17. Debug Support Signals (continued)
Signal Name
Abbreviation
Function
I/O
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