參數(shù)資料
型號： MCF52223CVM66J
廠商： Freescale Semiconductor
文件頁數(shù)： 14/55頁
文件大?。?/td> 0K
描述： IC MCU 32BIT W/USB 81MAPBGA
標準包裝： 240
系列： MCF5222x
核心處理器： Coldfire V2
芯體尺寸： 32-位
速度： 66MHz
連通性： I²C，SPI，UART/USART，USB OTG
外圍設備： DMA，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 56
程序存儲器容量： 256KB（256K x 8）
程序存儲器類型： 閃存
RAM 容量： 32K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 81-LBGA
包裝： 托盤
Family Configurations
MCF52223 ColdFire Microcontroller, Rev. 3
Freescale Semiconductor
21
1.3
Reset Signals
Table 5 describes signals used to reset the chip or as a reset indication.
1.4
PLL and Clock Signals
Table 6 describes signals used to support the on-chip clock generation circuitry.
1.5
Mode Selection
Table 7 describes signals used in mode selection; Table 8 describes the particular clocking modes.
Table 5. Reset Signals
Signal Name
Abbreviation
Function
I/O
Reset In
RSTI
Primary reset input to the device. Asserting RSTI for at least 8 CPU
clock cycles immediately resets the CPU and peripherals.
I
Reset Out
RSTO
Driven low for 1024 CPU clocks after the reset source has deasserted.
O
Table 6. PLL and Clock Signals
Signal Name
Abbreviation
Function
I/O
External Clock In
EXTAL
Crystal oscillator or external clock input except when the on-chip
relaxation oscillator is used.
I
Crystal
XTAL
Crystal oscillator output except when CLKMOD0=0, then sampled as
part of the clock mode selection mechanism.
O
Clock Out
CLKOUT
This output signal reflects the internal system clock.
O
Table 7. Mode Selection Signals
Signal Name
Abbreviation
Function
I/O
Clock Mode Selection
CLKMOD[1:0]
Selects the clock boot mode.
I
Reset Configuration
RCON
The Serial Flash Programming mode is entered by asserting the
RCON pin (with the TEST pin negated) as the chip comes out of
reset. During this mode, the EzPort has access to the flash memory
which can be programmed from an external device.
Test
TEST
Reserved for factory testing only and in normal modes of operation
should be connected to VSS to prevent unintentional activation of
test functions.
I
Table 8. Clocking Modes
CLKMOD[1:0]
XTAL
Configure the clock mode.
00
0
PLL disabled, clock driven by external oscillator
00
1
PLL disabled, clock driven by on-chip oscillator
01
N/A
PLL disabled, clock driven by crystal
10
0
PLL in normal mode, clock driven by external oscillator1
10
1
Reserved2
11
N/A
PLL in normal mode, clock driven by crystal1
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