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Chapter 18 Multiplexed External Bus Interface (MEBIV3)
MC9S12E128 Data Sheet, Rev. 1.07
Freescale Semiconductor
517
Detailed descriptions of these pins can be found in the device overview chapter.
PE5/IPIPE0/MODA
MODA
At the rising edge on RESET, the state of this pin is registered into the MODA
bit to set the mode.
PE5
General-purpose I/O pin, see PORTE and DDRE registers.
IPIPE0
Instruction pipe status bit 0, enabled by PIPOE bit in PEAR.
PE4/ECLK
PE4
General-purpose I/O pin, see PORTE and DDRE registers.
ECLK
Bus timing reference clock, can operate as a free-running clock at the system
clock rate or to produce one low-high clock per visible access, with the high
period stretched for slow accesses. ECLK is controlled by the NECLK bit in
PEAR, the IVIS bit in MODE, and the ESTR bit in EBICTL.
PE3/LSTRB/ TAGLO
PE3
General-purpose I/O pin, see PORTE and DDRE registers.
LSTRB
Low strobe bar, 0 indicates valid data on D7–D0.
SZ8
In special peripheral mode, this pin is an input indicating the size of the data
transfer (0 = 16-bit; 1 = 8-bit).
TAGLO
In expanded wide mode or emulation narrow modes, when instruction tagging
is on and low strobe is enabled, a 0 at the falling edge of E tags the low half of
the instruction word being read into the instruction queue.
PE2/R/W
PE2
General-purpose I/O pin, see PORTE and DDRE registers.
R/W
Read/write, indicates the direction of internal data transfers. This is an output
except in special peripheral mode where it is an input.
PE1/IRQ
PE1
General-purpose input-only pin, can be read even if IRQ enabled.
IRQ
Maskable interrupt request, can be level sensitive or edge sensitive.
PE0/XIRQ
PE0
General-purpose input-only pin.
XIRQ
Non-maskable interrupt input.
PK7/ECS
PK7
General-purpose I/O pin, see PORTK and DDRK registers.
ECS
Emulation chip select
PK6/XCS
PK6
General-purpose I/O pin, see PORTK and DDRK registers.
XCS
External data chip select
PK5/X19
thru
PK0/X14
PK5–PK0
General-purpose I/O pins, see PORTK and DDRK registers.
X19–X14
Memory expansion addresses
Table 18-1. External System Pins Associated With MEBI (continued)
Pin Name
Pin Functions
Description