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型號(hào)：	MC9S12E64MPVE
廠商：	FREESCALE SEMICONDUCTOR INC
元件分類：	微控制器/微處理器
英文描述：	16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP112
封裝：	LQFP-112
文件頁(yè)數(shù)：	348/606頁(yè)
文件大?。?/td>	3146K
代理商：	MC9S12E64MPVE

Chapter 12 Pulse-Width Modulator (PWM8B6CV1)

MC9S12E128 Data Sheet, Rev. 1.07

Freescale Semiconductor

To calculate the output frequency in center aligned output mode for a particular channel, take the selected

clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period

PWMx frequency = clock (A, B, SA, or SB) / (2*PWMPERx)

PWMx duty cycle (high time as a% of period):

— Polarity = 0 (PPOLx = 0)

Duty cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

— Polarity = 1 (PPOLx = 1)

Duty cycle = [PWMDTYx / PWMPERx] * 100%

As an example of a center aligned output, consider the following case:

Clock source = bus clock, where bus clock = 10 MHz (100 ns period)

PWMx frequency = 10 MHz/8 = 1.25 MHz

PWMx period = 800 ns

PWMx duty cycle = 3/4 *100% = 75%

Shown below is the output waveform generated.

Figure 12-39. PWM Center Aligned Output Example Waveform

12.4.2.7

PWM 16-Bit Functions

The PWM timer also has the option of generating 6-channels of 8-bits or 3-channels of 16-bits for greater

PWM resolution}. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.

The PWMCTL register contains three control bits, each of which is used to concatenate a pair of PWM

channels into one 16-bit channel. Channels 4 and 5 are concatenated with the CON45 bit, channels 2 and 3

are concatenated with the CON23 bit, and channels 0 and 1 are concatenated with the CON01 bit.

Change these bits only when both corresponding channels are disabled.

When channels 4 and 5 are concatenated, channel 4 registers become the high-order bytes of the double

byte channel as shown in Figure 12-40. Similarly, when channels 2 and 3 are concatenated, channel 2

registers become the high-order bytes of the double byte channel. When channels 0 and 1 are concatenated,

channel 0 registers become the high-order bytes of the double byte channel.

PERIOD = 800 ns

DUTY CYCLE = 75%

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