External Clock Operati" />
參數(shù)資料
型號: MC9328MXSCVP10
廠商: Freescale Semiconductor
文件頁數(shù): 68/74頁
文件大?。?/td> 0K
描述: IC MCU I.MXS 100MHZ 225-MAPBGA
標準包裝: 160
系列: i.MXS
核心處理器: ARM9
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SPI,SSI,UART/USART,USB
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 97
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 225-LFBGA
包裝: 托盤
Functional Description and Application Information
MC9328MXS Technical Data, Rev. 3
70
Freescale Semiconductor
External Clock Operation (Port B Alternate Function2)
15
STCK/SRCK clock period1
92.8
81.4
ns
16
STCK/SRCK clock high period
27.1
40.7
ns
17
STCK/SRCK clock low period
61.1
40.7
ns
18
STCK high to STFS (bl) high3
92.8
0
81.4
ns
19
SRCK high to SRFS (bl) high3
92.8
0
81.4
ns
20
STCK high to STFS (bl) low3
92.8
0
81.4
ns
21
SRCK high to SRFS (bl) low3
92.8
0
81.4
ns
22
STCK high to STFS (wl) high3
92.8
0
81.4
ns
23
SRCK high to SRFS (wl) high3
92.8
0
81.4
ns
24
STCK high to STFS (wl) low3
92.8
0
81.4
ns
25
SRCK high to SRFS (wl) low3
92.8
0
81.4
ns
26
STCK high to STXD valid from high impedance
18.9
29.07
16.6
25.5
ns
27a
STCK high to STXD high
9.23
20.75
8.1
18.2
ns
27b
STCK high to STXD low
10.60
21.32
9.3
18.7
ns
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
1.0
ns
30
SRXD hold time after SRCK low
0
0
ns
Synchronous Internal Clock Operation (Port B Alternate Function2)
31
SRXD setup before STCK falling
18.81
16.5
ns
32
SRXD hold after STCK falling
0
0
ns
Synchronous External Clock Operation (Port B Alternate Function2)
33
SRXD setup before STCK falling
1.14
1.0
ns
34
SRXD hold after STCK falling
0
0
ns
1 All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
2 There are 2 set of I/O signals for the SSI module. They are from Port C primary function (pad 257 to pad 261) and Port B
alternate function (pad 283 to pad 288). When SSI signals are configured as outputs, they can be viewed both at Port C primary
function and Port B alternate function. When SSI signals are configured as inputs, the SSI module selects the input based on
FMCR register bits in the Clock controller module (CRM). By default, the input are selected from Port C primary function.
3
bl = bit length; wl = word length.
Table 30. SSI (Port B Alternate Function) Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
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